Row grabbing system

ABSTRACT

A real time frame grabbing system for substantially instantaneously providing a continuous video display or a selectable predetermined video frame of information on a video display means from continuously transmittable video information which is transmitted as a plurality of pseudo video scan lines wherein the selected frame being grabbed is updatable on a displayable row by displayable row basis. Each of the pseudo video scan lines has a television scan line format and comprises a complete self-contained packet of digital information sufficient to provide an entire displayable row of video data characters, the pseudo video scan line having an associated transmission time equivalent to that of a television video scan line. The packet of digital information comprises at least address information for a displayable row and data information for the displayable characters in the row. Each of these psuedo video scan lines further comprises a horizontal sync signal at the beginning thereof which provides a record separator between adjacent pseudo video scan lines and resets the input receiver logic for the transmitted pseudo video scan lines upon the detection of each horizontal sync signal to provide noise immunity enhancement. The pseudo video scan lines are transmitted and received through a conventional television distribution system. Each pseudo video scan line contains means for error checking the contents of the received pseudo video scan line for inhibiting display of the associated displayable row when the error check is not satisfied. Programmable means, such as a general purpose digital computer, is conventionally programmed to interleave the pseudo video scan line signal transmission to provide pseudo video scan line information corresponding to a common assigned row for a plurality of frames before providing such information corresponding to a subsequent different common assigned row for the plurality of frames.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to video communication systems in whichindividual frames may be grabbed for video display thereof.

2. Description of the Prior Art

Video communication systems in which individual frames may be grabbedfor video display are well known, such as the system disclosed in U.S.Pat. No. 3,740,465, or a system employing the Hitachi frame grabbingdisc. These prior art systems such as the one disclosed in U.S. Pat. No.3,746,780 are normally two-way request response systems requiring theuser to request information by the dialing of a specific digital codewhich is uniquely assigned to each frame. However, such systems normallygrab a group of frames for storage and then subsequently select theindividual frame for display out of the group of grabbed frames asopposed to instantaneously selecting a single frame in real time.Furthermore, such prior art systems do not provide for real timeupdating of the grabbed video frame. Furthermore, some such prior artframe grabbing systems, such as the type disclosed in U.S. Pat. No.3,397,283 are normally capable of only grabbing the next immediatesignal in response to the provision of a starter signal or, as disclosedin U.S. Pat. No. 3,051,777, utilize a counter for frame location whichmust be reset to the beginning of a tape for video tape suppliedinformation in order to locate a selected frame to be grabbed. Thesesystems are not applicable in a real time frame grabbing environment.Similarly, other typical prior art frame grabbing systems, such asdisclosed in U.S. Pat. Nos. 3,695,565; 2,955,197; 3,509,274; 3,511,929and 3,582,651 can not be utilized in a real time frame grabbingenvironment, such as one in which the video information associated withthe grabbed frame is capable of being continuously updated. Accordingly,presently available prior art frame grabbing systems familiar to theInventors are not capable of easily locating a frame to be grabbed inreal time nor of being able to continuously update such a grabbed framein real time.

Video communication systems in which the signal being transmitted isdigitized are also well known. For example, U.S. Pat. No. 3,743,767discloses a video communication system for the transmission of digitaldata over standard television channels wherein the digital data istransmitted in a conventional television scan line format throughconventional television distribution equipment. However, such prior artcommunication system merely digitizes one television scan line at a timefor distribution to a video display terminal on a bit-by-bit basis in aline, 84 bits of information being provided per television scan line.Furthermore, such a prior art system is not transmission selectable byevery display terminal nor is the data for a displayable video rowpacked into a self-contained pseudo video scan line information packet.Thus, there is no significant increase in the data transmission rateresulting from such a prior art video communication system. Similarly,U.S. Pat. Nos. 3,061,672 and 3,569,617 are examples of other prior artvideo communication systems in which television signals are digitizedwithout any significant resultant compression in data transmission time.Furthermore, these other prior art systems require special distributioncircuitry. In addition, prior art video communication system in which adigital television signal is transmitted do not sufficiently isolate theindividual rows comprising a frame so as to provide satisfactory noiseimmunity between these rows, noise immunity at best being providedbetween frames, nor is there satisfactory data compression in thetransmission time of the video information in such prior art systems.

These disadvantages of the prior art are overcome by the presentinvention.

SUMMARY OF THE INVENTION

A real time frame grabbing system for substantially instantaneouslyproviding a continuous video display of a selectable predetermined videoframe of information on a video display means from continuouslytransmittable video information, wherein such information is transmittedas a plurality of pseudo video scan lines is provided. Each of thepseudo video scan lines has a television video scan line format andcomprises a complete self-contained packet of digital informationsufficient to provide an entire displayable row of video datacharacters, the pseudo video scan line having an associated transmissiontime equivalent to that of a television video scan line. The packet ofdigital information comprises at least address information, such aspage, group, permission, user and direct address for a displayable rowand data information for the displayable characters, such as 32characters, in a displayable row. Each of the pseudo video scan linesfurther comprises a horizontal sync signal at the beginning thereof,each horizontal sync signal providing a record separator betweenadjacent pseudo video scan lines as well as providing noise immunity ona row by row basis for resetting all the input logic in the receiverwhich processes the transmitted signal every horizontal sync pulse. Thetransmitter for the pseudo video can line includes means for providing avertical sync signal after a predetermined plurality of pseudo videoscan lines have been transmitted, the pseudo video scan line being acomposite video signal. These transmitted pseudo video scan linecomposite vieo signals are distributed through a conventional televisiondistribution system, such as a cable distribution system, to variousvideo display means for providing a continuous video display thereof.The receiver which is operatively connected between the distributionnetwork and an associated video display means, processes the distributedcomposite pseudo video scan line signals and provides a displayablevideo row to the associated video display means from each of the pseudovideo scan line signals pertaining to the frame selected in order toprovide the continuous video display, a predetermined plurality ofdisplayable video rows comprising a displayable video frame ofinformation. The receiver also preferably includes means for updatingthe continuously video displayable selectable frame on a displayablevideo row-by-row basis dependent on the real time data informationcontent of the received pseudo video scan line.

Each of the packets of digital information contained within the pseudovideo scan line, also preferably includes an error check informationcontent based upon at least the address and data information content ofthe associated pseudo video scan line, the receiver including errorcheck means for obtaining an error check indication of the distributedassociated pseudo video scan line and comparing the error checkindication with the error check information content of the associatedpseudo video scan line in accordance with a predetermined error checkcondition for providing a predetermined output condition when the errorcheck condition is satisfied. The receiver also includes conditionresponsive means operatively connected to the error check means forpreventing the provision of the displayable video row from theassociated pseudo video scan line when the predetermined outputcondition is not met.

The system also preferably includes programmable means, such as ageneral purpose computer, for receiving the continuously transmittablevideo information, retrievably storing the information, reformatting itinto a desired pseudo video scan line format and continuously providingthis reformatted information to the transmitter on a word-by-word basis,a word comprising a pair of displayable characters. Furthermore, theprogrammable means preferably includes means for interleaving thereformatted pseudo video scan line information to provide pseudo videoscan line information corresponding to a common assigned row for aplurality of frames to the transmitter before providing pseudo videoscan line information corresponding to a subsequent different commonassigned row for the plurality of frames to the transmitter. Thus, theprovision of the pseudo video scan line enables the use of conventionaltelevision transmission techniques and equipment for transmission andreception as well as conventional television circuitry for processingthe received and transmitted signals. Furthermore, by utilizing thehorizontal sync as a record separator, one can insure that any loss ofsynchronization or noise pulse will not disrupt more information thanone pseudo video scan line. In addition, significant data compression intransmission time is obtained by transmitting the pseudo video scanlines as opposed to conventional television scan lines, with each pseudovideo scan line being a self contained packet of information sufficientfor display of an entire displayable video row containing a plurality ofconventional television scan lines, such as 13, as opposed to display ofone television scan line.

In the present invention, frame grabbing is accomplished by preferablyfeeding the pseudo video scan line into a buffer storage for comparisonwith an information request from the .[.keyboarad.]. .Iadd.keyboard.Iaddend.which, if matched, updates the appropriate memory for displayor selection control so that updating is, in reality, accomplished on arow-by-row basis as opposed to a page or frame-by-frame basis as newinformation is provided in real time, the selected frame beingautomatically updated in real time as new information is provided for agiven row of the displayed selected frame.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagrammatic illustration of a typical pseudo video scanline format in accordance with the present invention;

FIG. 2 is a graphical illustration of conventional vertical drive andcomposite sync signals illustrating the origin of the vertical syncsignal in accordance with the present invention;

FIG. 3 is a .[.blcok.]. .Iadd.block .Iaddend.diagram of the timing andkeyboard control, memory input control and a part of the outputprocessing portions of the preferred receiver of the present invention;

FIG. 4 is a block diagram of the phase locked loop portion of thearrangement illustrated in FIG. 3;

FIG. 5 is a block diagram of another portion of the memory input controlportion of the preferred receiver of the present invention;

FIG. 6 is a block diagram of the memory and output processing portion ofthe preferred receiver of the present invention;

FIG. 6a is a graphical illustration of the timing associated withvarious signals in the arrangement of FIG. 6;

FIG. 7 is a block diagram of another portion of the memory and outputprocessing portion of the preferred receiver of the present invention;

FIG. 8 is a logic diagram, partially in schematic, of a portion of thetiming and keyboard control portion of the preferred receiver of thepresent invention illustrated in FIG. 3;

FIG. 9 is a logic diagram, partially in schematic, of the keyboardportion of the timing and keyboard control portion of the receiverillustrated in FIG. 3;

FIG. 10 is a logic diagram, partially in schematic, of the portion ofthe memory input control portion of the receiver illustrated in FIG. 5;

FIG. 11 is a logic diagram, partially in schematic, of the portion ofthe memory input control portion of the receiver illustrated in FIG. 6;

FIG. 12 is a logic diagram, partially in schematic, of the memory andoutput processing portion of the receiver illustrated in FIG. 3;

FIG. 13 is a logic diagram, partially in schematic, of another portionof the memory and output processing portion of the receiver illustratedin FIG. 7;

FIG. 14 is a block diagram of the preferred transmitter portion of thepresent invention;

FIG. 15 is a logic diagram of the first in-first out memory portion ofthe transmitter portion illustrated in FIG. 14;

FIGS. 16 and 17 are logic diagrams, partially in schematic of thetransmitter portion illustrated in FIG. 14 except for the first in-firstout memory portion illustrated in FIG. 15; and

FIG. 18 is a functional block diagram of the preferred embodiment of therow grabbing system of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT System GeneralDescription

Referring now to the drawings in detail and initially to FIG. 18thereof, the preferred embodiment of the row grabbing system, generallyreferred to by the reference numeral 10, of the present invention isshown. As will be described in greater detail hereinafter, the rowgrabbing system 10 of the present invention is preferably a one-wayframe grabbing system in which continuously transmitted information ormessages are transmitted via pseudo video scan lines 12 (FIG. 1 and 2)on a row by row basis, with the pseudo video scan line 12 preferablybeing identical in format to a conventional video scan line, that is itis consistent with FCC and EIA standards for a video scan line signalformat; however, this pseudo video scan line 12 actually contains a rowof information, such as approximately between 11 and 13 actualtelevision video scan lines of information, with the transmission timeof the pseudo video scan line 12 preferably being equal to thetransmission time of a conventional TV video scan line, which isapproximately 63 microseconds. The various portions of the pseudo videoscan line 12 will be described in greater detail hereinafter withreference to FIGS. 1 and 2. In the row grabbing system 10 of the presentinvention, the information is updated on a row by row basis bytransmission of a pseudo video scan line containing new information sothat the frame being grabbed will effectively have this row containingnew information updated when this row of information is updated inmemory. In the preferred system 10 of the present invention,continuously transmitted information or messages may be instantaneously"grabbed" in real time so as to repetitively provide a video display ofa selected video frame of such information which may be updated on a rowby row basis in real time.

Video information may be of any conventional type, such as newsinformation, money rate information, stock market information, localadvertising, television program listings, weather information, consumerinformation, etc., which is conventionally supplied from conventionalexternal information sources for these types of information such assources 2,002 and 2004 shown by way of example. These conventionalexternal information sources 2,002 and 2,004 preferably conventionallysupply this information in a digital format, such as from a ticker fornews information or stock information, by way of example, through aconventional communication line 2,006 or 2,008 or a conventional localvideo terminal, preferably, to a conventional mini computer 2000, suchas a model number PDP-8e manufactured by Digital Equipment Corp.Mini-computer 2000 preferably has an associated conventional mass memory2010 for conventional storage of data. Computer 2000 stores thisinformation in mass memory 2010, reformats it, such as by adding headerinformation, and continuously provides this information as a 12 bitparallel output 2011 to a transmitter 20, to be described in greaterdetail hereinafter, which provides the pseudo video scan line 12 fortransmission to the TV distribution network. It should be noted that atany time, the twelve bit parallel output of computer 2000 preferablyrepresents two characters or one word. If desired, a 14 bit parallel bitoutput from the computer 2000 could be utilized to provide two seven bitcharacters. Computer 2000 shall be described in greater detailhereinafter with reference to FIG. 14. The mass memory 2010 ispreferably updated by the computer 2000 in conventional fashion at theoptimum transfer time for data which is, conventionally, not necessarilyin the order of reception of the external information from sources 2002and 2004, this data being preferably continuously suppliable in realtime to the computer 2000. In conventional fashion, the information incomputer 2000 is supplied to transmitter 20 which, in turn, suppliesthis information to a CATV cable system 22 through a conventional RFmodulator 24, composite video being supplied to modulator 24 fromtransmitter 20. One such modulator 24 is preferably provided for eachtelevision channel on which information is to be transmitted, only onesuch channel being illustrated in FIG. 18 by way of example. Preferably,the mass memory 2010 which is read in conventional fashion by computer2000 to provide the requisite information via transmitter 20 to the CATVcable system 22, has sufficient storage capacity to store the entirepage capacity of the system.

As used hereinafter throughout the specification and claims the termpage means one video frame of information, the term group means apredetermined number of pages, the term row is a displayable video rowand means a portion of a page containing a plurality of conventionaltelevision video scan lines, and the term pseudo video scan line means asignal which is identical in form to that of a conventional video scanline but which actually contains a row of information, such asapproximately between 11 and 13 actual television video scan lines ofinformation with the transmission time of the pseudo video scan linebeing equal to the transmission time of a conventional TV video scanline and with the pseudo video scan line being an entire packet ofinformation necessary for video display of that row. The termconventional or television video scan line is used in its conventionalmanner.

The mass memory 2010 may be any conventional mass memory storage devicesufficient to store the requisite page capacity of the system, such asan RK-08 memory device manufactured by Digital Equipment Corp. Theoutput of the computer 2,000 is preferably conventionally transmittedfrom computer 2,000 to the transmitter 20 via a conventional data breakof the computer 2,000. All pages of information are preferablycontinuously being transmitted from the computer 2000 throughtransmitter 20 on a pseudo video scan line by pseudo video scan linebasis, that is respectively on a row by row basis, through theappropriate RF Modulator 24 for the video channel being utilized and,therefrom, through the CATV cable system 22 to conventional videodisplay terminals or devices 2013 and 2015, such as commerciallyavailable video monitors, two such devices being shown by way ofexample. It should be noted that the number of video display devices2013 and 2015 preferably has no requisite correlation with the number of.[.eternal.]. .Iadd.external .Iaddend.information sources 2002 and 2004and more sources 2002 and 2004 could be utilized than video displaydevices 2013 and 2015 or vice versa, if desired. In normal contemplateduse, the number of video display devices 2013 and 2015 will normallyexceed the number of external information sources 2002 and 2004,however, this need not be the case. The computer 2000 conventionallyrecirculates the data provided thereto in continuous fashion and, aspreviously mentioned, eventually updates the mass memory 2010 at theoptimum transfer time for the data, which time is not necessarily in theorder of reception of the external information from sources 2002 and2004. The information from external sources 2002 and 2004, which ispreferably being provided substantially continuously to the computer2000 (as long as it is being generated from the external sources 2002and 2004) is provided to the mass memory 2010 and instantaneously to thetransmitter 20 which operates in a manner to be described in greaterdetail hereinafter to provide the pseudo video scan line 12 transmissionof the information. As will also be described in greater detailhereinafter, each video display device 2013 and 2015 preferably has anassociated display control unit 25 and 26, respectively, which, as willbe described in greater detail hereinafter, preferably functions toenable the real time frame grabbing or selection of a single page ofcontinuously transmitted information for the instantaneous repetitivecontinuous video display, or frame grabbing, thereof, this informationbeing updatable on a row by row basis in real time. Preferably, each ofthe display control units 25 and 26 by way of example, one such displaycontrol unit preferably being associated with each video displayterminal or device, are identical in structure and operation. Ifdesired, however, any display control unit 25-26 may be modified in amanner to be described in greater detail hereinafter so as to preventthe reception of certain categories of information while enabling thereception of other categories of information. For purposes of clarity,only one such typical display control unit 25 will be described by wayof example, the structure and operation, as previously mentioned, beingidentical with that of display control unit 26. Identical referencenumerals, followed by the letter a will be utilized in FIG. 18 forelements of display control unit 26 which are identical in structure andoperation with those of display control unit 25. In the overall systemblock diagram of FIG. 18, the display control unit 25 only preferablycontains a conventional RF demodulator 27, one such demodulator 27 beingprovided for each channel and a receiver 28, to be described in greaterdetail hereinafter, which receiver receives the composite videodemodulated by demodulator 27 and determines whether the user iscorrect, the user has permission to receive the pseudo video scan lineof information being transmitted at that time, whether the signal iserror free, whether the page address of the pseudo video scan line iscorrect, and whether a direct address condition, to be described ingreater detail hereinafter, exists, and, preferably assuming the pseudovideo scan line signal passes all these tests, then the receiverprocesses this signal and provides a video signal corresponding to adisplayable row of information on the video display device 2013. Thekeyboard which accomplishes the selection of the desired page or videoframe of information and the appropriate group thereof to be grabbed orrepetitively displayed on the video display terminal 2013 is included aspart of the receiver portion 28 and will be described in greater detailhereinafter as part of the receiver portion 28 of the system 10.

TRANSMITTER General Description

Referring now to FIG. 14, initially, the transmitter portion 20 of therow grabbing system 10 of the present invention shall generally bedescribed in greater detail. Thereafter, with reference to FIGS. 15, 16and 17, the preferred transmitter portion 20 of the present inventionshall be described in greater detail.

Computer 2000 which provides the 12 bit parallel output 2011 of dataalso provides a strobe command, as will be described in greater detailhereinafter, via path 2014, the strobe command on path 2014 and the 12parallel lines of data 2011 being preferably loaded into a conventionalFIFO word series memory, shown in greater detail in FIG. 15, which actslike a parallel shift register. FIFO memory 2016 preferably acceptsinformation under command of the strobe line 2014 from computer 2000 andcan preferably store up to 64 words which is 128 characters ofinformation, two characters of information comprising one word. Computer2000 can .[.slo.]. .Iadd.also .Iaddend.preferably completely erase FIFOmemory 2016 by the provision of a reset command via path 2018, as willbe described in greater detail hereinafter. FIFO memory 2016 supplies aready signal to computer 2000 via path 2020 which denotes that the inputlocation of memory 2016 is empty. Computer 2000 only preferably strobesdata into FIFO memory 2016 if the ready line 2020 is asserted. It shouldbe noted that preferably the inputting and outputting of memory 2016 arecompletely independent of each other.

The transmitter 20 preferably includes a conventional television syncgenerator 2022 which provides composite sync via path 2023 in accordancewith EIA standards as well as vertical drive via path 2025. The timingof sync generator 2022 is preferably controlled by conventional crystalcontrolled oscillator 2026, such as a 14.31818 megahertz crystalcontrolled oscillator, in conventional fashion. The transmitter 20preferably requires a master clock to control the bit rate oftransmission. This bit rate, which is preferably selected at 5.113657megahertz, must preferably be synchronized with the composite sync. Thedata bit rate selected must be consistent with the broadcast televisionchannel .[.band width.]. .Iadd.bandwidth .Iaddend.and must be anintegral multiple of the horizontal frequency, which is necessary tokeep the data bits phase locked with the horizontal sync signal. The5.113657 megahertz clock, which shall be referred to as clock A, ispreferably obtained by a conventional crystal controlled phase lockedloop 2024 which is locked at 5/14 of the 14.31818 megahertz oscillator2026 frequency through a divide-by-14/5 frequency divider 2028. Theclock A output of phase locked loop 2024 is preferably divided by aconventional divide-by-seven bit counter 2030 in order to generate apulse on line 2032 which represents the start of each character. Thispulse is provided in parallel to a character counter 2034 which usesthis signal as a clock input and preferably counts up to 40, counter2034 being a divide-by-40 counter, to establish the period correspondingto the 40 characters preferably contained within a single pseudo videoscan line 12. The output of character counter 2034 is preferably a pulseon line or path 2036 which occurs during the period of the 40thcharacter. The trailing edge of the pulse present on path 2036preferably sets a flip-flop 2038 which is reset by the composite syncprovided via path 2023 from sync generator 2022. Thus, the output offlip-flop 2038 is a gate which starts at the end of the 40th characterand ends at the beginning of the horizontal sync pulse. During thisgating time, it is preferably desired to transmit a burst of sync pulseswhich are identical to a stream of alternate "0" and "1" data bits, thisburst of sync pulses being located in region F (FIG. 1) of the pseudovideo scan line 12, as will be described in greater detail hereinafter.This signal which is provided on line 2040 is termed the sync burst gateand is provided to a multiplexer 2042 as one input thereto, this inputbeing the control or select input for multiplexer 2042.

One selectable input to multiplexer 2042 is provided from the output ofa divide-by-2 flip-flop 2044 whose input is the clock A output of phaselocked loop 2024. When the gating signal on path 2040 is high,multiplexer 2042 preferably selects this input signal from flip-flop2044, which provides a square wave output at one-half the frequency ofclock A, and applies this signal to the output data line 2046 ofmultiplexer 2042. The other selectable input to multiplexer 2042preferably is the serial data output of a conventionalparallel-to-serial shift register 2050 which receives the 12 parallellines of data output from FIFO memory 2016. When the gate signal on path2040 is low, multiplexer 2042 preferably selects the serial data line2048 output from shift register 2050 and applies this signal to theoutput data line 2046 of multiplexer 2042. Shift register 2050 ispreferably a 14 line input parallel-to-serial shift register with twolines being grounded in the arrangemet to be described by way ofexample. If 14 input data lines were utilized then these two groundedterminals will, of course, be respectively connected to the other two ofthe 14 data input lines. Shift register 2050 receives the 12 lines ofdata from FIFO memory 2016 via path 2051, this data being loaded intoshift register 2050 when a load command is received from bit counter2030 on path 2032. Data is outputed from shift register 2050 as theserial data line 2048, the shift rate being preferably established byclock A. Preferably, 14 clock pulses occur to shift out 14 bits of datafrom shift register 2050 for each word loaded into shift register 2050.The data output of multiplexer 2042 is preferably supplied to aconventional sync combiner 2052 which also receives the composite syncsignal via path 2023 from sync generator 2022.

The output of sync combiner 2052 is a conventional composite videosignal format, which is a three level signal, the data varying betweenlevels 2 and 3 corresponding to digital values of 0 and 1 and the syncbeing indicated by level 1, as illustrated in FIGS. 1 and 2, with FIG. 1illustrating a typical pseudo video scan line signal 12 format. Thiscomposite video signal represents a single pseudo video scan line at atime as described and shown in FIGS. 1 and 2, computer 2000 beingconventionally programmed to control various locations or assignments inregions B through E of the pseudo video scan line, these regions to bedescribed in greater detail hereinafter in the description of thereceiver portion 28 of the row grabbing system 10. As was previouslymentioned, region F of the pseudo video scan line 12 is provided on line2040 as a sync burst gate provided to multiplexer 2042 and regions A andG are provided from the composite sync on path 2023.

The transmitter 20 also preferably includes a strobe control portion2054 which contains all the logic for determining when the data shouldbe strobed out of the FIFO memory 2016. It is most preferable that whendata is shifted out of memory 2016 and transmitted, that complete linesof 40 characters each are shifted, in the example given. If allconditions necessary for the transmission of 40 characters in a pseudovideo scan line 12 are not met preferably an empty line, which is apseudo video scan line having only regions A,F and G occupied, istransmitted. It is further preferred that data be transmitted onlyduring a selected portion of the television vertical frame so as toinsure that only empty lines are transmitted during the vertical driveperiod. Strobe control portion 2054 preferably monitors the variousconditions necessary and starts to issue a series of strobe out pulseson line 2056 only if the output of FIFO memory 2016 is ready asindicated on ready line 2058 provided from memory 2016 to strobe controlportion 2054, if the vertical scan position is correct as indicated by asignal present on line 2060 termed frame enable, to be described ingreater detail hereinafter, and if a composite sync pulse has beenreceived from sync generator 2022 via path 2023. When all theseconditions are met, the output of bit counter 2030 on line 2032 isallowed to control the strobing of FIFO memory 2016. The master resetpulse when issued or provided on line 2018 from computer 2000 preferablyprevents any new pseudo video scan line of data from being transmitteduntil all the above mentioned conditions are again met. The correctvertical scan position or frame enable signal provided via path 2060 ispreferably obtained from a decoder 2062 which decodes the output of aline counter 2064. Line counter 2064 counts the number of pseudo videoscan lines after the vertical drive, the inputs to line counter 2064being the vertical drive signal from sync generator 2022 provided viapath 2025 and the composite sync signal from sync generator 2022provided via path 2023. This decoder 2062 preferably selects the groupof lines which are used for transmission.

DETAILED DESCRIPTION OF TRANSMITTER

Referring now to FIGS. 15, 16 and 17, the transmitter portion 20 of therow grabbing system 10 of the present invention shall be described ingreater detail, FIGS. 15 through 17 being logic schematics ofappropriate portions of the transmitter portion 20, the balance of thetransmitter portion 20 not illustrated in greater detail than in FIG. 14being conventional. Accordingly, a more detailed description thanpreviously provided will not be provided for those conventional portionsnot illustrated in greater detail in FIGS. 15 through 17 as they wouldreadily be understood by one of ordinary skill in the art.

Referring initially to FIG. 15, the conventional FIFO memory 2016 isshown in greater detail. FIFO memory 2016 preferably comprises threeconventional four bit-by-64 word FIFO serial memories 2070, 2072 and2074, such as an MOS FIFO serial memory of the type manufactured byFairchild under designation 33414, each memory stage 2070, 2072 and 2074receiving four of the 12 parallel bit data line outputs from computer2000. The input ready and output ready lines are preferably combined byNAND gates 2076 for the input ready line to provide the input readysignal via path 2020 to computer 2000, and by NAND gate 2078 for theoutput ready line to provide the output ready signal via path 2058 tostrobe control portion 2054.

Referring now to FIGS. 16 and 17, the balance of the transmitter portion20 shall be described in greater detail, where appropriate, for purposesof clarity. Referring initially to FIG. 16, the television syncgenerator 2022, as previously mentioned, is preferably a conventionalMOS television sync generator such as the type manufactured by Fairchildunder the designation 3261 and will not be described in any greaterdetail herinafter. Oscillator 2026, which supplies the clock signal tothe television sync generator 2022 for controlling the timing thereofand the reference frequency signal to the phase locked .[.group.]..Iadd.loop .Iaddend.2024 .[.preferably.]., as previously mentioned,preferably comprises a conventional integrated circuit oscillator 3000,such as the type manufactured by Motorola under the designation 4024,utilized with inverters 3002 to 3004 to provide the clock to syncgenerator 2022 at opposite phases as is conventionally required by async generator 2022 of the type previously described. In addition,oscillator 3000 is preferably crystal controlled by a conventionalcrystal 3006 at the oscillator frequency, such as the 14.31818 megahertzfrequency chosen by way of example. The clock signal output ofoscillator 3000 is preferably applied via path 3010 to a conventionalfour bit binary counter 3008, such as the type manufactured by TexasInstruments under the designation SN 74161N, preferably connected as adivide-by-14 counter, counter 3008 forming a portion of thedivide-by-14/5 divider network 2028. The output of counter 3008 ispreferably connected as the clock input to a conventional divide-by-2flip-flop 3012 also forming part of the divide-by-14/5 divider 2028. Theoutput of the divide-by-2 flip-flop 3012 is preferably connected to oneinput of phase locked loop 2024 which is preferably a conventional MOSphase locked loop, such as the type manufactured by Signetics under thedesignation NE562B. Thus, the total division ratio from oscillator 2026through phase locked loop 2024 is preferably 28-to-1. The output ofphase locked loop 2024 provided via path 3014 is fed back to the inputof a conventional four bit binary counter 3016, such as the typeutilized for counter 3008, however counter 3016 preferably beingconnected as a divide-by-5 counter. The output of counter 3016 ispreferably, in turn, connected to a conventional divide-by-2 flip-flop3018, such as the type manufactured by Texas Instruments underdesignation SN 7474N, whose output is in turn preferably connected to asecond input of phase locked loop 2024. Accordingly, the total feed backpath division ratio is preferably 10 and the phase locked loop 2024,accordingly, varies its output frequency provided via path 3014 asnecessary to keep its two inputs from flip-flop 3012 and flip-flop 3018at exactly equal frequencies but with a phase difference of 90°. As aresult of the frequency division ratio utilized on each input path tophase locked loop 2024, the phase locked loop output frequency isexactly preferably 5/14 of the frequency of oscillator 2026 which, byway of example, provides a clock A output frequency for phase lockedloop 2024 of 5.1136357 megahertz as the output frequency of phase lockedloop 2024.

Bit counter 2030 which, as previously mentioned with reference to FIG.14, preferably receives this clock A output frequency, is preferably aconventional divide-by-7 bit binary counter 3020, such as the typemanufactured by Texas Instruments under the designation SN74160N,counter 3020 which forms part of the bit counter network 2030 preferablybeing the actual bit counter. Two of the output lines of bit counter3020 are preferably decoded by a conventional two input NAND gate 3022to provide a pulse at the third count of counter 3020, this pulse beingprovided as one input to a two input negative NAND gate 3082. The carryoutput from bit counter 3020 is preferably connected to the D input of aconventional D type flip-flop 3024 whose clock input is preferablyconnected to the clock A output of phase locked loop 2024 provided viapath 3014. This provides at the output of flip-flop 3024 a pulse at thecompletion of the divide-by-seven cycle of counter 3020 which pulse isutilized as the load input of the parallel-to-serial register 2050provided via path 2032.

As was previously mentioned with reference to FIG. 14, the output of bitcounter 2030 provided via path 2032 is also preferably provided to.[.charcter.]. .Iadd.character .Iaddend.counter 2034. As shown andpreferred in FIG. 16, character counter 2034, which is preferably adivide-by-40 counter, comprises two counter stages 3026 and 3028 whichare both conventional four bit decade or divide-by-10 counters, such asthe type manufactured by Texas Instruments under the designationSN74160N. Each counter 3026 and 3028 is preferably clocked from themaster clock A via path 3014 and is enabled by the carry output of bitcounter 3020 via path 2032. Thus the counter stages 3026 and 3028preferably increment only once per character. The character counter 2034also preferably comprises a decoder which includes negative NAND gates3030 and 3032, connected, respectively, to the outputs of counter stages3026 and 3028, and a NAND gate 3034 whose inputs are the outputs ofgates 3030 and 3032. The decoder formed by gates 3030, 3032 and 3034preferably generates a negative pulse on the 40th count from counterstages 3026 and 3028 of counter 2034. As shown and preferred, counterstages 3026 and 3028 are cleared by the composite sync signal providedfrom sync generator 2022. The composite sync output of sync generator2022, as shown and preferred in FIG. 16, is provided to a conventional Dflip-flop 3036, with the composite sync output of sync generator 2022being provided to the D input thereof, flip-flop 3036 preferably beingclocked by the master clock A provided via path 3014. As a result, theoutput of flip-flop 3036 is preferably exactly the same as the inputcomposite sync from generator 2022 except that it is slightly delayed bya small fraction of the clock period, such as on the order of 50nanoseconds, as necessary for transitions of the output to be exactlysynchronized to the master clock frequency.

As was previously mentioned with respect to FIG. 14, multiplexer 2042preferably receives as one selectable input, the output of a divide-by-2flip-flop 2044 whose input is the master clock A output of phase lockedloop 2024. As shown and preferred in FIG. 16, flip-flop 2044 ispreferably a conventional flip-flop which has the inverted clock Asignal supplied to the clock input thereof through inverter 2045 andwhich generates an output frequency of one-half the clock A frequencyvia path 2047 to multiplexer 2042. The other selectable input tomultiplexer 2042, as was previously mentioned with respect to FIG. 14,is the serial data output of parallel-to-serial register 2050 providedvia path 2048. As shown and preferred in FIG. 16, parallel-to-serialregister 2050 preferably comprises two shift register stages 3038 and3040, such as the type manufactured by Texas Instruments underdesignation SN74166N, which are preferably loaded in parallel and areshifted out alternately, first seven bits being provided from one stageand then seven bits being provided from the other stage. The outputs ofshift register stages 3038 and 3040 are preferably alternately selectedby NAND gates 3042 and 3044. Preferably, the least significant bit ofdecade counter 3026 of character counter 2034 is supplied to one inputof NAND gate 3042 and is applied inverted through inverter 3043 to oneinput of NAND gate 3044. This signal preferably alternates at thecharacter rate and selects which NAND gate 3042 or 3044 is on. Theoutputs of NAND gate 3042 and 3044 are connected as the two inputs to anegative NOR gate 3046 and, accordingly, alternate groups of seven databits appear at these two inputs and a continuous stream of data bits is,therefore, present at the output of gate 3046 via path 2048 tomultiplexer 2042.

As was previously mentioned with reference to FIG. 14, the switching ofmultiplexer 2042 is preferably accomplished by flip-flop 2038, which ispreferably a conventional RS flip-flop which is set by the compositesync on one input via path 3050 and is reset by the output of NAND gate3034 of character counter 2034 which is the character 40 pulse. As shownand preferred in FIG. 16, multiplexer 2042 comprises NAND gates 3052 and3054 whose outputs are connected to negative NOR gate 3056. The selecteddata exists on output line 2046, gate 3052 and 3054 being supplied fromopposite outputs of flip-flop 2038 so that one of these two gates is onwhen the other is off and vice-versa.

Now referring to the strobe control logic 2054, this logic preferablyincludes a conventional flip-flop 3060 which is cleared by the masterreset signal provided via path 2018 from computer 2000 or by an outputpulse from a conventional counter 3062, to be described in greaterdetail hereinafter, contained within the strobe control logic 2054,provided via path 3063. Flip-flop 3060 is preferably set by thehorizontal sync. The output of flip-flop 3060 is preferably connected toone input of a three input NAND gate 3064 whose two other inputs areprovided from the frame enabling circuit or decoder 2062, to bedescribed in greater detail hereinafter with reference to FIG. 17. Theoutput of NAND gate 3064 will preferably be low during frame enable ifflip-flop 3060 is set. This output is preferably combined with the FIFOready signal in a negative NAND gate 3066 whose output will be high onlyif FIFO memory 2016 is ready as indicated by the FIFO ready signalprovided via path 2058, both frame enable signals are asserted and ahorizontal sync pulse has been received since the last or previoustransmission, as indicated by an output being provided from NAND gate3064 to negative NAND gate 3066. If all these conditions are met, gate3066 will provide an output signal to the D input of anotherconventional flip-flop 3068 which will be set at the start of the nexthorizontal sync pulse present at its clock input. When flip-flop 3068 isset, this signifies that the system is ready to start transmitting apseudo video scan line. The output of flip-flop 3068 is preferablyconnected to the clock input of another flip-flop 3070 which is,accordingly, set at the time that flip-flop 3068 is set. When flip-flop3070 is set, its output goes high enabling counter 3062 which thenstarts to count under control of the master clock A, provided via path3014, which is supplied at its clock input. Counter 3062 is preferably aconventional four bit divide-by-16 counter, such as the typemanufactured by Texas Instruments under the designation SN74163N. Whencounter 3062 counts to 8, its most significant bit goes high whichsupplies a high level signal via path 3071 to one input of aconventional two input NOR gate 3072. Gate 3072 then provides an outputsignal to a two input negative NAND gate 3074 which, in turn, providesan output signal to a two input NAND gate 3076 whose output is, in turn,inverted through an inverter 3078 to provide the FIFO .[.out.]. strobe.Iadd.out .Iaddend.signal via path 2056 to FIFO memory 2016. Whencounter 3062 counts to 15, its carry output preferably goes high and isfed back to flip-flop 3070 via path 3079 to clear it which in turnclears counter 3062 ending its count cycle. Thus, counter 3062preferably supplies a single FIFO strobe out pulse to FIFO memory 2016via path 2056 in the manner previously described at the beginning of apseudo video scan line. The purpose of this is to preferably preloadFIFO memory 2016 with the first valid word before transmission starts.Subsequent FIFO strobe out pulses are obtained from a negative NAND gate3082 which generates a strobe out pulse when a negative pulse is presentto gate 3082 from decoder 3022, which was previously described withreference to bit counter 2030, as long as a horizontal sync pulse is notpresent at its other input, the output of gate 3082 being the otherinput to NOR gate 3072. The second input to negative NAND gate 3074 ispreferably supplied from the negative output of flip-flop 3068 whichpreferably inhibits a strobe pulse after 40 characters have beentransmitted. The other input to NAND gate 3076, which is supplied fromthe counter stage 3026 through inverter 3043 to NAND gate 3076,preferably inhibits alternate pulses, pulses at the other input of NANDgate 3076 provided from the output of negative NAND gate 3074 occurringonce per character whereas a FIFO strobe out pulse is needed only onceper two characters, which is once per word.

Referring now to FIG. 17, the sync combiner 2052, frame enable decoder2062 and line counter circuit 2064 shall be described in greater detailhereinafter. The line counter 2064 preferably comprises two four bitbinary counter stages 3090 and 3092, such as the type manufactured byTexas Instrument under the designation SN74193L. Counter stages 3090 and3092 are preferably initially cleared by the vertical drive signal fromsync generator 2022 provided via path 2025 and are clocked by thecomposite sync signal from sync generator 2022 provided via path 2023via a conventional two input NAND gate 3094, the other input to NANDgate 3094 being the frame enable A signal output of decoder 2062provided via path 3095. Clocking of counter stages 3090 and 3092preferably continues until count 224 at which time decoder 2062, whichis preferably a three input NAND gate, generates a low output via path3095 turning off NAND gate 3094, NAND gate 2062 being the decoder whichprovides the frame enable signals via path 3095 and 3093, the frameenable signal provided via path 3093 being provided in parallel from oneinput to NAND gate 2062 from counter stage 3092 of line counter 2064.

Sync combiner 2052 which ultimately combines the composite video outputpseudo video scan line signal 12, is preferably a conventional synccombiner as shown and preferred in FIG. 17, and has a data input viapath 2046 and a composite sync input via path 2023, each of these inputssupplying current drive to a conventional transistor 3096 such that thecollector output via path 3097 of transistor stage 3096 has a currentdetermined by the combination of input logic levels and has three outputlevels corresponding to three signal levels, data varying between levels2 and 3 corresponding to digital values of 0 and 1 and sync beingindicated by level 1, this composite video signal output of path 3097representing one pseudo video scan line at a time as described and shownwith reference to FIGS. 1 and 2. This is the video signal transmittedfrom transmitter 20 to RF modulator 24 and therefrom through the cabledistribution network 22 from which it is ultimately demodulated andprovided to receivers 28 for processing and ultimate provision to thevideo display devices 2013 and 2015 for display of the selected orgrabbed frame as well as row-by-row update of the selected frame.

RECEIVER General Description

Referring now to FIGS. 3 through 7, initially, and once again to FIGS. 1and 2, the preferred receiver portion 28 of the row grabbing system 10of the present invention shall generally be described in greater detail.Thereafter, with reference to FIGS. 8 through 14, the preferred receiverportion 28 of the present invention shall be described in greaterdetail. As was previously described with reference to the preferredtransmitter portion 20 of the row grabbing system 10 of the presentinvention, the transmitter 20 preferably provides what is generallytermed a pseudo video scan line such as the type 12 illustrated inFIG. 1. This pseudo video scan line 12, as was previously described, isidentical in format to a conventional video scan line; that is, it isconsistent with FCC and EIA standards for a video scan line signalformat; however, this pseudo video scan line 12 actually contains a rowof information, such as approximately between 11 and 13 actualtelevision video scan lines of information with the transmission time ofthe pseudo video scan line 12 being equal to the transmission time of aconventional TV video scan line, which is approximately 63 microseconds.With respect to the pseudo video scan line 12, the horizontal sync andvertical sync portions are identical to a conventional video signal asis the format for the horizontal sync and the vertical sync as well asthe horizontal sync amplitude. The time and amplitude envelope of thevideo region of the pseudo video scan line 12, which region is definedas areas B,C,D,E and F in FIG. 1 is identical with the format for aconventional video scan line as is the three dimensional frequencyenvelope. Thus, all of the above mentioned standard conditions for aconventional video scan line signal are met by the pseudo video scanline 12 provided by the transmitter portion 20 of the row grabbingsystem 10 of the present invention and received by the receiver portion28. Accordingly, any .[.euipment.]. .Iadd.equipment .Iaddend.that canhandle conventional video can handle the pseudo video scan line 12 ofthe present invention which can thus be transmitted and received througha conventional television distribution system with conventionaltelevision equipment.

Referring once again to the pseudo video scan line 12 illustrated inFIG. 1, the signal received by the receiver portion 28 and transmittedby transmitter 20 is in reality a digital signal which looks like aconventional video scan line to the receiver 28. The distribution ofinformation in regions A through G of the pseudo video scan line, or rowof information, illustrated in FIG. 1 is as follows. Region A representsthe horizontal sync signal which starts the timing for the receiver 28and indicates the beginning of the pseudo video scan line from thebeginning of the horizontal sweep for a conventional television scanline. Region B represents the pseudo video scan line 12 address whichcontains all the following information bit locations. It should benoted, that preferably a 1 is indicated by the presence of a pulse and a0 is indicated by the absence of a pulse, such as illustrated in FIG. 1in region F where 1-0-1 is illustrated. When data is transmitted, as waspreviously mentioned, all of the following information bits are present;group, which is the section or chapter including a predetermined number,such as 1,000, of pages and is the most significant bit of the pageaddress, page which represents one frame in a group; and row whichoccupies one character space which is preferably seven bits, and definesa portion of a page preferably containing approximately 11 to 13 scanlines which comprise one displayable character height. Region B alsopreferably contains direct address information, which is the firsttransmitted bit preferably and is a 0 unless the direct addresscondition exists which is a control condition for a selected terminalinforming the terminal to supersede the requested page. This region alsopreferably contains permission information which is a one bit positionwhich is preferably a 1 when the user is being given authority toreceive one or more selected groups of information. It should be notedthat preferably there is also an emergency override condition whichprovides control information to all terminals to override all requestsincluding a permission request and occurs when the page and groupinformation bit locations are 0, this condition preferably beingutilized to display emergency information such as a civil defencewarning Region C is preferably a special character information region of7 bits which is preferably utilized for optional functions to beperformed by the individual receiver 28 or terminal. Region D preferablycontains 32 characters of displayable information in digital form.Region E preferably contains 7 bits of error check information and,preferably may represent the complement of the binary equivalent of thesum of all of the 1 bits present in regions B, C, and D. Region Fpreferably contains the clock synchronizing burst or pulse train at thebit rate (the frequency preferably being equal to one-half the bit-rate)and comprises a pulse train of ones and zeros of two character spaces or14 bits. Region G is preferably the same as region A and represents thehorizontal sync signal. As was previously mentioned, the vertical syncis provided by generating a special sequence of horizontal sync pulsesduring the normal television blanking period, which is afterapproximately 246 horizontal sync pulses, which in the present inventionis after approximately 20 pages have been transmitted. Therefore, a 20pages are transmitted before each vertical sync. The sync signal lookslike a conventional composite sync signal with the vertical syncinterval comprising approximately nine normal horizontal sync pulsetimes as illustrated in FIG. 2 which is an illustration of conventionalcomposite sync and vertical drive signals.

Now referring to FIGS. 3 and 4, the preferred synchronization and timingportion of the receiver portion 28 of the row grabbing system 10 of thepresent invention shall generally be described. The synchronization andtiming portion preferably contains a conventional sync separator 400which is provided in conventional fashion, through a conventionaldistribution system 22, with the composite video input via path 402 fromthe transmitter 20. As was previously mentioned, the composite videoinput provided via path 402 preferably includes data and horizontal syncinformation as well as vertical sync information at the appropriategiven time. The conventional sync separator 400 separates the compositevideo input signal into a vertical sync signal via path 404, ahorizontal sync signal via path 406 and a data signal via path 408, thedata signal via path 408 preferably including regions B through F for agiven pseudo scan line of information which is received via path 402 bythe sync separator 400. The data portion of the pseudo of the pseudovideo scan line 12 is provided in parallel as one input to aconventional two input NAND gate 410. The other input to NAND gate 410preferably comprises the character 39 and the character 40 pulse outputsignals of a counter and decoder circuit 412 to be described in greaterdetail hereinafter with reference to FIG. 8. Suffice it to say at thistime that an output is present to NAND gate 410 from the counter anddecoder circuit 412 during the time interval corresponding to characters39 and 40, as will be described in greater detail hereinafter. Theoutput of NAND gate 410 is provided to a conventional phase locked loop414, to be described in greater detail hereinafter with reference toFIGS. 4 and 8. Suffice it to say that phase locked loop 414 ispreferably a correctable voltage controlled oscillator which operateswithout any additional input, as illustrated in FIG. 4, at the data bitrate, which is preferably, by way of example, approximately 5.11megahertz, and is preferably crystal controlled. As illustrated in FIG.4, the phase locked loop 414 preferably comprises a conventional phase.[.dectector.]. .Iadd.detector .Iaddend.416, a conventional filter 418connected to the output of the phase detector 416 and a conventionalvoltage controlled oscillator 420 which is conventionally crystalcontrolled by crystal 422 which is connected to the output of filter418. In addition, a feedback path is conventionally provided between theoutput of voltage controlled oscillator 420 and the phase detector 416through a conventional divide-by-two flip-flop 424. Thus, a referencefrequency, which is half the data bit rate is provided to the phasedetector 416 and the output of the voltage controlled oscillator 420 isthe master clock frequency, termed clock A at the data bit rate. By wayof example, the reference frequency is approximately 2.55 megahertz andthe clock A frequency is approximately 5.11 megahertz. Thus, the clock Aoutput is provided via path 426 from the conventional phase locked loop414.

Referring once again to FIG. 3, the clock A output provided via path 426is provided to a conventional selectable divide-by-8 or divide-by-1frequency divider 428 (FIG. 6) whose output is either the clock A signalor the clock B signal which is the clock A signal divided by eight.Thus, for example, clock B is approximately 0.64 megahertz and isprovided via path 430 (FIG. 6). This clock B signal provided via path430 from selectable frequency divider 428 is preferably provided as aninput to the counter and decoder circuit 412 which preferably decodesthe character positions and the bits within the character by countingclock pulses starting with the end of the horizontal sync pulse, as willbe described in greater detail hereinafter, seven counts preferablybeing provided per character. The horizontal sync input is alsopreferably provided to the counter decoder circuit 412 to start and/orreset the counters contained therein. The output of the counter anddecoder circuit 412 is preferably the control information correspondingto character positions 1 through 41 and bits 1 through 7, by way ofexample. As was previously mentioned, the character position controlinformation for character positions 39 and 40 is preferably provided asone input to the two input NAND gate 410. It should be noted thatpreferably character positions 39 and 40 are the 14 bits which compriseregion F of the pseudo video scan line 12. Accordingly, NAND gate 410only preferably provides an output to phase locked loop 414 when thedata portion of the pseudo video scan line 12 is at region F so thatonly information contained in region F is provided to phase locked loop414. As was previously mentioned, region F is the reference frequencywhich is one-half the data bit rate or one-half the master clockfrequency which is supplied to the phase detector 416 whichconventionally functions together with the feed back signal from thevoltage controlled oscillator 420 as modified by the flip-flop 424 toprovide a feedback frequency equal to the reference frequency whichcorrects the voltage controlled oscillator 420 if there is anydifference, whether this difference be in frequency or phase. Inaddition, circuit 418 conventionally functions to stabilize the phaselocked loop 414, the output of the phase locked loop 414 being acontinuous clock signal which is twice the reference frequency andidentical in phase. Preferably, the data bit rate is equivalent to twicethe maximum frequency of transmission, with the highest frequency oftransmission possible being two bits per cycle for a digital signal.

The data information portion of the pseudo video scan line 12 is alsopreferably provided in parallel to an error check circuit 432 whichpreferably receives control or timing information from the counter anddecoder circuit 412 via path 434 corresponding to character position 38as well as receiving data via path 408 from the sync separator 400. Aswas previously mentioned, character position 38 preferably correspondsto the error check information portion of the pseudo video scan line 12.Error check circuit 432, will be described in greater detail hereinafterwith reference to FIG. 8 with respect to the presently preferredarrangement for accomplishing an error check. With respect to thearrangement illustrated in detail in FIG. 8, error check circuit 432preferably counts the number of "one" bits in characters 1 through 7which comprise regions B, C, and D, preferably, and compares that sumwith the binary number located in character position 38, whichcorresponds to region E, and requires non-coincidence in every bit ofthat comparison since character position 38 or region E preferablycontains the complement of that sum. Error check circuit 432 provides anoutput signal, such as a 1 , indicating the error check is OK when thepreferred error check condition exists, this signal being termed "errorcheck OK signal" provided via path 436. This error check OK signal onpath 436 will preferably remain until the next error check of the nextsubsequent pseudo video scan line which occurs one conventionaltelevision video scan line transmission time after the previous pseudovideo scan line. The complement of this sum is preferably selected froman .[.erro.]. .Iadd.error .Iaddend.check sum to allow a check for emptylines, which are lines that only contain information in regions F and Gwhich, in such an instance, would sum to 0. If the complement was notutilized for the error check sum in region E, such a signal would passthe error check since the sum would be 0 and character position 38 wouldcontain a 0 so the sum would match. Therefore, by utilizing thecomplement, empty line signals would be rejected, which is preferred inthe present invention.

The output of the counter and decoder circuit 412 also preferablycomprises a character clock signal for the main memory write mode, aswill be described in greater detail hereinafter with reference to FIG.8, which is provided to a conventional two bit multiplexer 440 whichalso receives as inputs a character clock signal in the main memory readmode from a column counter 442 (FIG. 7) to be described in greaterdetail hereinafter, via path 444, and a select input via path 446 whichsignal selects between the character clock input in the write mode andthe character clock input in the read mode in response to the provisionof a memory read/write signal from memory write logic 450 (FIG. 6), tobe described in greater detail hereinafter, via path 446. Preferably, inresponse to a memory write command which is provided from the memorywrite logic 450 via path 446, the character clock input selected bymultiplexer 440 is the signal provided from the counter and decodercircuit 412, whereas in response to a memory read command provided fromthe memory write logic 450, the character clock input selected bymultiplexer 440 is the character clock provided from column counter 442.The character clock input selectively provided from multiplexer 440 isused to clock a character counter 454, to be described in greater detailhereinafter with reference to FIG. 12, which also receives thehorizontal sync input to start and/or reset the counter 454. The outputof the character counter 454 is the character address. The data portionof the pseudo video scan line 12 provided via path 408 is also providedin parallel to a conventional serial memory 456 which is a one linebuffer which preferably delays the signal by one conventional televisionvideo scan line transmission time (preferably for character positions 4through 37, by way of example) before the provision of the data to amain memory portion 458 to be described in greater detail hereinafter.This delayed data is also provided in parallel via path 460 to apermission memory 462 (FIG. 6), to be described in greater detailhereinafter. This one conventional television video scan linetransmission time delay enables the testing, to be described in greaterdetail hereinafter, of the pseudo video scan line 12 for purposes ofdeciding whether or not to write this infomation into a main memory 464of the main memory portion 458 prior to the actual writing of the datainto this main memory 464. The actual generation of the read/writecommand to the main memory 464 will be described in greater detail withreference to FIGS. 5 and 6.

With reference to the main memory portion 458 of FIG. 3, the serialmemory 456 preferably has a 256 bit capacity and serially loads thesebits one character or seven bits at a time into a conventional shiftregister 466, which is a one word serial-to-parallel converter whichcomprises a conventional seven bit shift register which parallel unloadsseven bits into a character latch 468, to be described in greater detailwith reference to FIG. 12 or into a row latch 470 to be described ingreater detail hereinafter with reference to FIG. 12, depending on theparticular character position. As was previously mentioned, preferablycharacters 4 through 37 which represent, preferably, regions B, C, and Dof the pseudo video scan line 12 are loaded into the serial memory 456.Preferably, character latch 468 and row latch 470 are enabled by enablesignals provided from counter and decoder circuit 412 at the appropriatetimes. Preferably, row latch 470 receives character position 4information, which preferably comprises the row information andcharacter latch 468 preferably receives character positions 6 through37, which comprises region D, which preferably is the character ordisplayable data information. Preferably, as was preferably mentioned,the special character is located at character position 5 and is notunloaded to character latch 468. In addition, shift register 456receives the clock B input signal as a clock signal therefor. The outputof character latch 468 preferably provides a displayable data input inparallel to memory 464 one character at a time or seven bit parallel. Inthe memory write mode, row latch 470 will preferably provide the rowaddress in parallel to memory 464 for a given pseudo video scan line 12,which row address is preferably set once per pseudo video scan line 12.In the memory write mode, the row latch 470 output is provided to aconventional multiplexer 474 which switches the address input of memory464 to the output of row latch 470. In the memory read mode, multiplexer472 siwtches the row address input of memory 464 to the output of rowcounter 474 (FIG. 7), to be described in greater detail hereinafter.Preferably, five bits of row address are utilized which is adequate forproviding address information for 32 video displayable rows. As waspreviously mentioned, the main memory 464 address input identifies thecharacter address or character position which is provided from theoutput of character counter 454, which is preferably a five bit countercapable of supplying 32 character addresses utilizing the characterclock input (one clock per character) and the horizontal sync to providethe character addres. Accordingly, memory 464 is preferably, by way ofexample, a row-by-32 character array or page, of which 16 or 32 rows maybe utilized. Memory 464 receives a read or write command via path 446from memory write logic 450 (FIG. 6), as will be described in greaterdetail hereinafter. It should be noted that preferably four bits areutilized to assign 16 rows and one bit is utilized to assign a leftcontrol condition and a right control condition if 64 characters are tobe displayed instead of 32 characters, assuming a page has normally beendefined as 32 characters wide by 16 rows high, 64 charactersrepresenting two pages. It should also be noted that row latch 470 alsoprovides a permission bit output via path 480 to the permission writelogic 482 (FIG. 6), to be described in greater detail hereinafter.

Preferably, as was previously mentioned, the group and/or page to bedisplayed or grabbed in real time is selected by means of a conventionalkeyboard 484, to be described in greater detail hereinafter. Suffice itto say at this time that keyboard 484 is preferably a conventional tendigit keyboard which provides a serial digital output. For example, ifdecimal 326 is the number depressed on the keys of the keyboard 484,then keyboard 484 will conventionally put out a pulse train of 326pulses. The outputs from keyboard 484 are preferably the control signal"group call" provided via path 486, the "number" selected provided viapath 488, the control condition "up" or more provided via path 490 whichrepresents incrementing the selected number by one preferably; thecontrol condition "down" or back provided via path 492 which preferablyrepresents decrementing the selected number by 1; and the controlcondition "page call" provided via path 494, the control conditions upand down incrementing or decrementing the group or page selectiondepending on which condition, group or page, was most recently selected.This keyboard 484 output via paths 486 through 494, inclusive, ispreferably provided to a .[.key board.]. .Iadd.keyboard .Iaddend.counter500 (FIG. 5), to be described in greater detail hereinafter, where thisinformation is interpreted to control the selection of the appropriateframe to be grabbed in real time.

Referring now to FIGS. 5 and 6 the generation of the memory read/writecommand provided via path 446 and a memory write clock provided via path995 from memory write logic 450 shall generally be described. As waspreviously mentioned, the output of keyboard 484 is provided to keyboardcounter 500, to be described in greater detail hereinafter, which countsthe pulse train corresponding to the number selected and provides aparallel binary output, such as preferably 10 bits, for both the groupselected via parallel paths 502 and for the page selected via parallelpaths 504, and increments or decrements the appropriate counter inresponse to the receipt of the up or down control signal from thekeyboard 484. The selected page output 504 from keyboard counter 500 ispreferably provided in parallel to a conventional multiplexer 506 whichsequentially switches each parallel output 504 to a single output line508 to provide a serial selected page address on path 508. Multiplexer506 is addressed to switch by a page address counter 510 to be describedin greater detail hereinafter with reference to FIG. 10, which is inturn operated by the page address clock provided via path 512 fromcounter and decoder circuit 412 (FIG. 3), this page address clockpreferably being 10 bits or pulses which correspond to the page addressbits. The output of the page address counter 510 is preferably a binarynumber representing the bit number within the page address sequence andcontrols the switching of multiplexer 506. Multiplexer 506 and pageaddress counter 510 are preferably equivalent to a 10 bit parallelload/serial out shift register. The page address counter 510 andmultiplexer 506, as will be described in greater detail hereinafter,permit the page address to be checked. In order to accomplish this, theserial page address output on path 508 is provided as one input to aconventional exclusive or gate 514 whose other input is the page addressbit present on the data line 408, the serial page address bits on path508 being provided in coincidence with the page address bits on dataline 408. When the pseudo vidso scan line page address on data line 408is the same as the serial page address on path 508, the output ofexclusive or gate 514 will be low, which in the logic chosen by way ofexample represents a 0. When these inputs differ, in other words whenthere is a lack of coincidence, the output of exclusive or gate 514 willbe high (a 1 in the logic chosen) for at least one clock period of thepage address sequence. The output of exclusive or gate 514 is providedto a conventional flip-flop 516 which, when the output of 514 is high,will be clocked by the page clock provided via path 512. Flip-flop 516is preferably a conventional JK flip-flop. If at any time during thepage address sequence, the output of 514 goes high, the output offlip-flop 516 will preferably go low and provide no output and remainlow until reset by the horizontal sync at the end of the pseudo videoscan line 12. The normal condition of the output of flip-flop 516provided via path 518 is a high or 1 indicating that the page address isOK or checks, this signal being termed the "page address OK signal"which is provided to another conventional flip-flop 520 (FIG. 6) whichsupplies this information to the memory write logic 450.

Now considering the provision of a user address check to insure that thecorrect user is receiving the pseudo video scan line. The page addresscounter 510 output is also provided in parallel to multiplexer 522 whoseother input is a hard-wired user address 524. The user addressperferably occupies the same space in the pseudo video scan line as thepage address and, accordingly, the receiver 28 must preferably be ableto distinguish between the two. The page address counter 510 outputsequentially switches multiplexer 522 to provide a serial bit useraddress on path 526 to EXCLUSIVE OR GATE 528 whose other input is thedata path 408. The serial user address provided via path 526 is incoincidence with the user address bits provided via path 408 to gate528. When the pseudo video scan line user address provided via path 408is the same as or coincident with the user address provided via path526, the output of gate 528 will be low for the logic chosen by way ofexample. When there is a lack of coincidence between these two inputs togate 528, the output of gate 528 will be high for at least one clockperiod of the user address sequence. The output of gate 528 ispreferably provided to a conventional JK flip-flop 530 which ispreferably clocked by the page address clock provided via path 512. Ifat any time during the user address sequence, which is preferablyidentical with the page address sequence, the output of gate 528 goeshigh, the output of flip-flop 530 will preferably go low (a no outputcondition) and remain low until reset by the horizontal sync, providedvia path 406, at the end of the pseudo video scan line. The normalcondition of the output of flip-flop 530 is preferably high on path 532indicating that the user address checks or is OK, indicated by the term"user address OK signal" which is provided as one input to thepermission write logic 482 (FIG. 6). The user address O.K. signal isalso provided to memory write logic 450 through a flip-flop 960, viapath 961, which preferably introduces a one scan line delay.

Now considering the direct address condition we refer once again to FIG.5. As was previously mentioned, the first bit of the address in region Bof the pseudo video scan line 12 is preferably the direct address bit. Abit one gate signal is provided as an output from a decoder 940,942(FIG. 10) via path 534 and is termed the "bit one gate" output. Thisoutput is provided to a conventional flip-flop 536 which senses whetherthis signal is a 1 or 0. Flip-flop 536 provides an output signal "directaddress OK" on path 538 when the first bit is a 1. The data line inputfrom sync separator 400 provided via path 408 is provided to flip-flop536 which is clocked by the bit one gate output on path 534 from decoder412. The output of flip-flop 536 provided via path 538, which output istermed the direct-address-OK-signal when a direct address condition ispresent, is preferably provided to another conventional flip-flop 540(FIG. 6) whose output is connected as one input to the memory writelogic 450 to be described in greater detail hereinafter.

Referring now to FIG. 6, the generation of the read/write main memorycommand via path 446, the main memory write clock via path 995 and thegeneration of the permission memory read/write command from thepermission write logic 482 shall be described in greater detailhereinafter. As was previously mentioned, the permission bit of the rowaddress position is provided via path 480 from the row latch 470 to thepermission write logic 482, as is the user address OK signal on path 532from flip-flop 530. Permission write logic 482 preferably stores theuser address OK signal and delays it for one conventional televisionvideo scan line transmission time as illustrated in FIG. 6a. If thedelayed user address OK signal is present at the same time thepermission bit signal is present on path 480, permission write logic 482preferably provides a permission write command signal via path 550 tothe permission memory 462 and, in parallel, to a conventionalmultiplexer 552 as a select signal thereto. Permission memory 462preferably receives data input via path 460 from the output of serialmemory 456 (FIG. 3). In the write mode for the permission memory 462 viapath 550, multiplexer 552 selects the address input for permissionmemory 462 from the parallel output of a bit counter 554 which providesone input to multiplexer 552, the other selectable input to multiplexer552 being the selected group parallel bit output 502 of keyboard counter500. The input to the bit counter 554 is the clock B output of thedivide-by-8 or divide-by-1 frequency divider 428, with the divide-by-8or divide-by-1 mode selected by the condition of line 550. In thepermission write mode, frequency divider 428 is preferably set as adivide-by-8 counter so that the output in this mode is the clock Boutput comprising the clock A input divided by 8 or, in the examplegiven, approximately 0.64 megahertz. This clock-A-divided-by-8 output offrequency divider 428 in this permission write mode is preferably alsoutilized as the clock input for the serial memory 456. As a result, thepermission memory 462 address is preferably changed coincident with theshifting of the input data, both occurring at the reduced clock B rate.It should be noted that the permission bit only identifies one pseudovideo scan line of data as a permission line but is not the actualpermission indication, all data of that pseudo video scan line havingthe permission bit comprising the permission data or indication. It isthis permission data which is provided to the permission memory 462 viapath 460. The permission data provided via path 460 to permission memory462 preferably contains information as to which group the user haspermission to receive. Each bit of permission data pertains to adifferent group, preferably, and is stored in permission memory 462addressable by bit. For example, if one starts counting with thebeginning of the fifth character position, if the 24th bit in the pseudovideo scan line obtaining permission information after the start of thecount was a 1, that bit would be present at the input of permissionmemory 462 at the time that the address input to permission memory 462was the binary number 24. Therefore, when in the permission read mode,if the address is 24, that would be output on line 556 as a permissionOK signal. The above, is thus an example of giving permission for group24. Preferably, the permission memory 462 is non-destructible and, ispreferably constructed to operate at the reduced address rate, theclock-A-divided-by-8 rate being the preferred standard inexpensive MOSmemory (for example a Signetics 2602B) operating rate. However, becauseof utilizing the reduced operating rate of clock-A-divided-by-8, ittakes 8 pseudo video scan lines of time to perform this permissionwriting operation. This can, however, be conventionally scheduled byconventional programming of a computer to avoid any noticeable lag (dueto interleaving) since any given terminal or receiver 28 does notnormally receive all successive pseudo video scan lines as eachsuccessive scan line preferably pertains to a different page. Forexample, as previously mentioned, the sequence of transmission ispreferably page 1, line 1, page 2, line 1, etc. until all the pages haveline 1 thereof transmitted and then page 1, line 2, page 2, line 2,etc., until all the pages have line 2 transmitted and so forth untileach line of each page has been transmitted. Thus, the pseudo video scanlines of one page are preferably interleaved with the pseudo .[.vido.]..Iadd.video .Iaddend.scan lines of another page so that a directfull-page-by-full-page transmission does not occur; rather thetransmission is preferably one row per page at a time.

Now describing the permission read mode and referring once again to FIG.6, the permission read condition on line 550 is the opposite conditionfrom the permission write condition occurring on line 550. In thepermission read mode, the selected group information 502 provided fromkeyboard counter 500 to multiplexer 552 is the address input which isprovided to permission memory 462, this input 502 having been selectedby multiplexer 552 which has been switched by the permission read signalappearing on line 550. If this address input 502 to permission memory462 is a permitted group, then a permission OK signal, such as a 1, willbe present on line 556. For example, if, as in the previous example,group 24 was selected, then a permission OK signal would be present online 556. Accordingly, the operation of permission memory 462 is aconventional look-up table operation.

The page address OK signal present on path 518 is provided to flip-flop520 to introduce a delay equivalent to the transmission time for oneconventional television video scan line. Similarly, the direct addressOK signal which would be present on line 538 is introduced to flip-flop540 to introduce a delay equivalent to the transmission time for oneconventional television video scan line. As shown and preferred in FIGS.6 and 6a, all single television video scan line delay outputtransmissions provided by the permission write logic 482, flip-flop 520and flip-flop 540 occur at the time of the occurrence of the character41 timing signal from decoder 412. As is also shown and preferred inFIG. 6, the delayed page address OK signal flip-flop 520 output isprovided via path 560 to the memory write logic 450, the delayed directaddress OK signal output from flip-flop 540, when such a signal ispresent, is provided via path 562 to the memory write logic 450 and thedelayed (one scan line) error check OK signal is provided via path 436to the memory write logic 450. In addition, the permission OK signal isprovided via path 556 to the memory write logic 450. As will bedescribed in greater detail hereinafter, the main memory write commandsignal is provided to multiplexer 440 via path 446 when the error checkOK signal is present on path 436 and either the direct address OK signalis present on path 562 or both the page address OK signal is present onpath 560 and the permission OK signal is present on path 556. When theseconditions are met, the memory write command signal is provided via path446 to multiplexer 440.

Referring once again to FIG. 3, the provision of data 564 from mainmemory 464 as well as the loading of the main memory 464 shall bediscussed. The main memory write clock signal provided via path 995 tomain memory 464 preferably causes memory 464 to input data from theserial memory buffer 456 in the following write cycle. As was previouslymentioned, the input data to memory 464 is one pseudo video scan line 12of data. Serial memory 456 provides the data one character or seven bitsat a time serial to shift register 466. Shift register 466 in turnprovides this data to character latch 468 seven bits parallel. While thenext seven bits of the next character are being shifted into shiftregister 456 from serial memory 456, the first seven bits previouslyloaded into the character latch 468 are loaded into the memory 464. Thiscycle continues preferably 32 times to load all characters of one row,which is a psuedo video scan line, into memory 464. At that time, thewrite cycle is complete. The write cycle begins anew when another mainmemory write clock signal is received by memory 464 and all otherpreviously mentioned conditions are met.

In the read mode, a main memory read command signal is provided tomultiplexer 440 via path 446. This memory read command signal conditionis present on path 446 when the memory write command signal condition isnot present as it represents the opposite conditions for line 446. Thecharacter address is provided from character counter 454 to main memory464 in the same manner as previously discussed with respect to the writemode. Main memory 464 provides the parallel bit data output 564 tocharacter generator 570 (FIG. 7), to be described in greater detailhereinafter, as addressed by row and character. This parallel bit dataoutput 564 is preferably a seven bit parallel representation ofalphanumeric characters, such as an ASCII code of both upper and lowercase letters, or just upper case letters and special symbols forgraphics or other purposes such as chemical symbols, stock marketfraction symbols, etc.

Now referring to FIG. 7, the display of decoded data such as charactersand symbols shall generally be described. It should be noted that,preferably, the operation of the circuitry illustrated in FIG. 7 ispreferably that of a conventional television digital display terminal.For purposes of discussion, it shall be assumed that a row of pseudovideo scan line 12 contains 13 conventional television video scan linesof data, although, if desired, such a system could utilize 11conventional television video scan lines or some other acceptablequantity. It should be noted that in the same time as 13 horizontal syncsignals are received in the example given, 13-times-13 conventionaltelevision video scan lines are received, since each pseudo video scanline contains, in the example given, 13 conventional television videoscan lines of information, the transmission time of a pseudo video scanline being equivalent to the transmission time of a conventional TVvideo scan line. However, since only 13 conventional television videoscan lines can be displayed in this time interval, the receiver portion28 receives 13 times as much information as can be displayed at anygiven time. The horizontal sync signal is provided via path 406 to aconventional divide-by-13 binary counter 572 which counts 13 horizontalsync signals in order to establish a row. Line counter 572 preferablyprovides a parallel bit output 574 representing the line number within arow as it counts and at the end of the 13th count provides a pulse viapath 576, termed the row clock, to row counter 474 indicating the end ofa row. This pulse via path 576 is, accordingly, used as a clock for rowcounter 474, the sequence being counter 572 counts to 13, advances onerow and restarts counting to 13 again. Line counter 572 and row counter474 are reset by the vertical snyc signal provided via path 404 fromsync separator 400 each new vertical scan. The output 578 of row counter474, as was previously mentioned, becomes the row address for mainmemory 464 in the read mode thereof through multiplexer 474 whichswitches the row address input from the row latch 470 to the row counter474 in the main memory read mode so that correspondence between data inmemory 464 and the vertical position on the video diplay screen isestablished.

The displayable character are preferably defined by the seven parallelbit output data 564 from main memory 464 and preferably each consist ofa 7-by-9 character matrix which is nine matrix lines high by sevencolumns wide. Preferably, one additional blank column is provided in thedisplayable matrix so as to provide an 8-by-9 displayed matrix. Thedisplayable characters are conventionally generated by defining a 1 or a0 to each of the 63 points in the 7-by-9 character matrix. The output ofthe character generator 570 is seven lines corresponding to seven bitsof one matrix line of the 7-by-9 character matrix. The line address 574provided to the character generator 570 from line counter 572conventionally determines which of the nine matrix lines in the 7-by-9character matrix is presented at the output of character generator 570.This output is provided to a conventional multiplexer 580 whichsequentially switches along the parallel inputs 582 from charactergenerator 570, plus one grounded input 584 which allows for the blankcolumn to provide an eight bit wide displayable matrix as discussedabove, to provide a serial output of one matrix line in the 8-by-9displayable matrix, the eight column being blank in order to allow forspacing between characters. Multiplexer 580 is preferably operated bycolumn counter 442 which is a divide-by-8 conventional counter which isclocked by clock B. Column counter 442 preferably counts clock B pulsesfor 8 bits which is the width of the displayable matrix. It should benoted that all characters in a row preferably have the same charactermatrix line addressed first before the next character matrix line ofthat row is addressed. In other words, matrix line 1 for each of the 32characters in a row is addressed first before matrix line 2 of any ofthe characters is addressed, and so forth. Column counter 442, as waspreviously mentioned, also provides the character clock via path 444 tocharacter counter 454 through multiplexer 440 in the memory 464 readmode.

The serial output of multiplexer 580 is a true displayable videocharacter, this character not being a true displayable video signaluntil output from multiplexer 580. The output of multiplexer 580provided via path 590 is preferably the only true video present duringthe times corresponding to the 32 characters of width and the 16 rows ofheight preferably comprising a page. During the time outside this regionor envelope there is an undesirable information content for conventionalpurposes. Therefore, it is preferably desired to eliminate thisundesirable content. Accordingly, the video output signal of multiplexer580 provided via path 590 is supplied to one input of a two inputconventional NAND gate 592. A conventional blanking logic arrangement594, to be described in greater detail hereinafter, supplies the otherinput to NAND gate 592 via path 596 to provide an enabling gating signalto NAND gate 592 to allow the video signal output present on path 590 tobe provided via path 598 to the video display device 2013, 2015conventional video circuitry only during the time corresponding to validcharacters as a function of horizontal and vertical position. Blankinglogic 594 is controlled in response to the vertical sync provided viapath 404 from sync separator 400, to the row counter 474 via a signalprovided via path 600 to blanking logic 594, a signal provided fromcolumn counter 442 via path 602 to blanking logic 594. The character 3and character 40 output signals from decoder 412 which are provided atthe times of the occurrence of the third character and the fortiethcharacter in the pseudo video scan line 12 and the main memory readwrite command signal provided from the memory write logic 450, thiscommand signal turning off the video during the write mode of the memory464.

DETAILED DESCRIPTION OF RECEIVER

Referring now to FIGS. 8 through 14, which are logic schematics of thevarious portions of the receiver 28, the receiver portion 28 shall bedescribed in greater detail, where necessary, with respect to structureand operation.

Referring now to FIG. 8, a logic schematic of the circuitry generallyshown in block form in FIGS. 3 and 4 is shown. Referring initially tothe phase locked loop 414, the phase detector 416, filter 418 andvoltage control oscillator 420 are preferably formed on a conventionalMOS integrated circuit 650, such as a Signetics NE 562b phase lockedloop chip, with flip-flop, 424 and crystal 422, which is preferably a5,113,636 hertz crystal for the frequency utilized in the example given,being conventionally connected to appropriate circuit connections onchip 650.

Referring now to the counter and decoder circuit 412, illustrated ingreater detail in FIG. 8, the generation of the various appropriatecharacter position timing signals shall be described in greater detail.Decoder circuit 412 preferably comprises three four bit decade counters652, 654 and 656, with decade counter 652 preferably being conventionalarranged as a divide-by-7 counter and with counters 654 and 656 beingconventionally arranged as divide-by-10 counters. These counters 652,653, and 656 are preferably conventional decade counters, such as thetype manufactured by Texas Instruments under designation SN74160N decadecounters. Because decade counter 652 is a divide-by-10 counter arrangedas a divide-by-7 counter, the horizontal. sync presents counter 652 atcount 3 to count from 4 through 10 for a total of seven counts. However,if a conventional divide-by-7 counter were utilized, if desired, insteadof a modified divide-by-10 counter, then this counter would be preset to0. The conventional modification to decade counter 652 to provide adivide-by-7 counter therefrom is provided by a NOR gate 658 connected tothe load input of counter 652. Counter 652 is preferably chosen as adivide-by-7 counter so that its cycle corresponds to one character, thebinary output of counter 652 representing the bit number within acharacter, which preferably comprises seven bits, by counting the clockB' input to counter 652. At the completion of the seventh count, counter652 preferably generates a pulse which is used to enable counter 654which only counts a clock B' pulse when enabled by counter 652.Therefore, counter 654 only counts characters, one enabling pulse beingprovided per seven bit character from counter 652. The output of counter654 preferably enables counter 656 which functions together with counter654 as a two digit character counter 660, each of counters 654 and 656preferably having a four wire BCD output. It should be noted that,preferably, counter 654 contains the least significant digit and counter656 contains the most significant digit of the two digits. These BCDoutputs are preferably connected to conventional BCD-to-decimal decoders662 and 666, respectively, such as integrated circuit BCD-to-decimaldecoders of the type manufactured by Texas Instruments under designationSN7442AN. It should be noted that decoder 664 is preferably for the 10position and decoder 662 is preferably for the ones position so that, byway of example, if the two digit output is the character 38 indicatingcharacter position 38, then it would be a 3 output from decoder 664 andan 8 output from decoder 662. Accordingly, decoders 662 and 664preferably provide a decimal output of the character position whilecounter 652 provides the binary output of the bit position within acharacter.

The various gating and flip-flops illustrated in FIG. 8 which areconventionally associated with the outputs of decoders 662 and 664 andcounter 652 conventionally provide the output signals representative ofcharacter position and bit position within a character in accordancewith the desired bit and character output timing signals from counter652 and decoders 662 and 664 required for the balance of the circuitry.As will be described in greater detail hereinafter, by way of example,the critical timing signals shall be chosen as those for characterpositions 38, 39, 40, 41, bit 7 of character 40, character positions1,2,3,4,5 and 6, the first bit of the 7 bit count of counter 652 and thelast 2 bits of this 7 bit count. Before describing the generation ofthese character position timing signals, it should be understood thatthe gating scheme illustrated in the figures and particularly in FIG. 8,is merely illustrative, by way of example, of a typical bit assignmentof a pseudo video scan line 12 which could be varied to any desirablebit assignment with appropriate conventional modification to thecircuitry so as to select a different set of appropriate timing signals.The 38th character position timing signal is present on path 670 and isprovided when decoder 664 provides a 3 to negative NAND gate 672. The39th character position timing signal is present on path 676 and isprovided when a 3 is provided from decoder 664 via path 674 to negativeNAND gate 678 and a 9 is provided from decoder 662 to gate 678. The 40thcharacter position timing signal is provided on path 680 from negativeNAND gate 682 when a 4 is provided from decoder 664 via path 684 and a 0is provided from decoder 662 to gate 682. The 41st character positiontiming signal is provided on path 686 from negative NAND gate 688 when a4 is provided from decoder 664 on path 684 to 688 and a 1 is providedfrom decoder 662 to gate 688.

A conventional four input NAND gate 690 has one input connected to path680 from gate 682 which provides an output during the occurrence of the40th character position for the pseudo video scan line 12, and the otherthree inputs thereto connected to the outputs of bit counter 652. NANDgate 690 preferably provides an output on path 692 when the binarynumber 7 is present on the three output lines of counter 652 and the40th character position timing signal is present on path 680 from gate682 which is only present for the seventh bit of the 40th character.This output is inverted through conventional inverter 694 and providedto a conventional flip-flop 696 whose output in the set state is thedata gate signal present on path 698. The two least significant bitoutputs of counter 652 are preferably connected in parallel to anotherconventional NAND gate 700 whose output on path 702 is preferably onlylow when the first bit of the 7 bit count is present, this output beingprovided as one input to negative NOR gate 704 whose other input isconnected through an inverter 706 to the most significant bit output ofcounter 652, which input is present only for the last two bits of the 7bit count of counter 652. The output of gate 704 is termed the "loadmemory" signal which is provided via path 708. In addition, the mostsignificant bit output of counter 652 is connected in parallel via path710 to provide what is termed the "change memory address" signal on path710 which is present for the last two bits of the 7 bit count of counter652. As was previously mentioned, the data gate output signal providedvia path 698 from flip-flop 696 is set by the 4th character positiontiming signal provided as the output of negative NAND gate 712 whoseinputs are the digit 0 from decoder 664 and the digit 4 from decoder662. Flip-flop 696 is preferably reset by the seventh bit of the 40thcharacter which is the signal provided via path 692, shown as inverted,by way of example, for the logic chosen by way of example. This datagate output is provided on path 698 when flip-flop 696 is in the setstate. In addition to providing the set state for flip-flop 696, theoutput of negative NAND gate 712 which is the character 4 positiontiming signal, is provided in parallel via path 714 to provide the rowgate signal and as one input to a two input NOR gate 716 whose outputvia path 718 is the video gate signal provided during the 1,2,3 and 4characters of the pseudo video scan line 12, the other inputs to NORgate 716 being the character 1, 2 and 3 position timing signals providedfrom negative NOR gate 720 through a two input NAND gate 722 whose otherinput is the 0 output of decoder 664, with the inputs to gate 720 beingthe digit 1,2 and 3 decoded outputs of decoder 662.

The page address clock output on path 512 is preferably present forcharacter positions 1, 2 and 3 and is gated on during these charactertimes, this output signal being provided from a NAND gate 724 which hasone input connected in parallel via path 726 to the output of NAND gate722 which is the present during character positions 1,2 and 3, the otherinput connected via path 728 to the output of a conventional single-shot730. Single-shot 730 is preferably fired by the leading edge of theclock B' input pulse to insure symmetry in the clock pulse, the pulseduration of single-shot 730 preferably being set at one-half the clockB' pulse period to insure this symmetry so that single-shot 730 actuallyreproduces the clock B pulse. Thus, the clock B pulse is, in reality,the clock B' pulse reconstituted by single-shot 730 in conventionalfashion.

Decoder 412 also provides a latch gate output signal via path 732 as theoutput of a two input NAND gate 734 whose inputs are the clock B' pulseand the carry output of the divide-by-seven counter 652 so that thelatch gate output signal on path 732 is the clock B' output as gated bythe completion of the most significant bit count, which is the seventhbit count, of counter 652. Decoder 412 also preferably provides a memorygate output signal on path 740 from another conventional flip-flop 742which is preferably set by the character 6 position timing signal viapath 744 and reset by the character 39 position timing signal via path746. Flip-flop 742 provides the memory gate output signal on path 740 inthe set state. The character 6 position timing signal via path 744 isprovided at the output of a negative NAND gate 750 whose two inputs arethe digit 0 of decoder 664 and the digit 6 of decoder 662 with thecharacter 39 position timing signal provided via path 746 to flip-flop742 being the signal provided via path 676 but inverted by inverter 752.

Now referring to FIG. 8 and describing the presently preferred errorcheck circuit 432. Error check circuit 432 preferably comprises aconventional JK flip-flop 760 which receives the clock B input fromsingle-shot 730 via path 762 and also receives the data input from inputdata line 408. The output of flip-flop 760 will preferably follow theinput data line except that it will be synced with the clock B signal bythe clocking of flip-flop 760. The output of the flip-flop 760 isprovided as one input to a two input NAND gate 766 whose other input isthe clock B input provided in parallel via path 762. Thus, NAND gate 766has one clock pulse output for each 1 bit on the data line 408, thepresently preferred method of error checking being to count the 1 bitspresent on the data line 408. In order to accomplish this counting,error check circuit 432 preferably includes two four bit cascadedconventional binary counters 770 and 772, such as the IC typemanufactured by Texas Instruments under designation SN74161N which countthese 1's to preferably provide a maximum count of 256 bits. Counters770 and 772 are preferably initially reset by the horizontal snyc signaland are enabled to count preferably through character position 37. Thecounting of counter 770 and 772 is preferably inhibited for characters38 and 39, this inhibiting signal being provided via path 780 from theoutput of a conventional two input NOR gate 782, with one input beingprovided thereto via path 676 for the character 39 position and theother input being provided thereto via path 670 for the character 38position. In the example given, the character 38 position for the pseudovideo scan line 12 is preferably the error check position of region E.Therefore, during the occurrence of character positions 38 and 39, aparallel binary output is provided from counters 770 and 772 whichrepresents the total number of 1 bits counted up through the character37 position, this output being present or continually provided as oneinput to a conventional exclusive or comparator 784 and 786,respectively, such as the IC type manufactured by Texas Instrumentsunder designation SN7468N. The data line input provided via path 408 ispreferably provided in parallel as an input to a conventional shiftregister 790, such as a Texas Instrument SN74164N type, which is clockedby the clock B pulse as gated on by the character 38 position timingsignal so that shift register 790 is preferably only clocked during theoccurrence of the 38th character position. Therefore, at the completionof the 38th character, the check sum contained therein is provided as aparallel binary output to comparators 784 and 786, respectively. Aspresently preferred, the check sum is the complement of the number of 1bits contained in the pseudo video scan line 12. If every bit of thecheck sum provided to comparator 784-786 from shift register 790 is thecomplement of the bit count provided to comparator 784-786 from counters770 and 772, respectively, then each output line of comparators 784 and786 will preferably be high. If all these lines are high, this indicatesthat the error check is OK. A NAND gate 794 is connected to the parallelbit output of comparator 784 and another NAND gate 796 is preferablyconnected to the parallel bit output of comparator 786. The output ofNAND gates 794 are 796 are preferably connected to the inputs of a twoinput negative NAND gate 798 whose output is the error check OK signalprovided via path 800 to one input of a two input NAND gate 802. Gates794, 796 and 798 conventionally provide logical anding of the comparator784-786 outputs, gate 798 preferably only having an output when eachoutput of comparator 784 and 786 is high. Therefore, the output of gate798 is an error check OK signal on path 800 at the completion of the38th character, which is during the occurrence of the 39th character.NAND gate 802 preferably samples path 800 during the 39th character sothat if there is an error check OK signal present on path 800 duringthis time, the other input to NAND gate 802 being the 39th characterposition timing signal via path 676, then NAND gate 802 will provide anegative pulse error check OK signal on path 804 to a conventionalflip-flop 806 which gets set by the presence of the negative pulse viapath 804 corresponding to the error check OK signal and provides anoutput signal which is the error check OK signal provided via path 436.Flip-flop 806 preferably holds this state unitl the start of the 38thcharacter of the next pseudo video scan line 12 which is indicated bythe presence of a signal on path 808 from shift register 790. Thissignal resets flip-flop 806 and the cycle previously described repeatswhen the 39th character comes up in the next pseudo video scan line 12if a valid error check is present.

Now the selectable divide-by-8 or divide-by-1 frequency divider 428(FIG. 6) shall be described in greater detail with reference to FIG. 8.The frequency divider 428 preferably comprises a conventionaldivide-by-8 counter 810, such as a Texas Instruments SN74161N. Thiscounter 810 receives the clock A master clock frequency via path 426from the voltage controlled oscillator portion of chip 650 and generatesa clock A-divided-by-8 signal via path 812 as one input to a two inputNAND gate 814. The other input to NAND gate 814 is the permission writesignal provided via path 550b. Another conventional two input NAND gate816 receives as one input the clock A master frequency input in parallelvia path 426 and as the other input the inverted permission write signalinput provided via path 550b as inverted by invertor 818. NAND gate 816preferably provides the clock A output to a two input negative .[∪]..Iadd.OR gate .Iaddend.820 when the permission write signal is notpresent on path 550b and NAND gate 814 preferably provides the clock Adivided-by-8 output to negative .[.or.]. .Iadd.OR .Iaddend.gate 820 whenthe permission write signal is present on path 550b. Negative .[∪]..Iadd.OR gate .Iaddend.820 provides a clock output termed clock B' onpath 822 which is equivalent to whichever output is being provided tonegative .[∪]. .Iadd.OR gate .Iaddend.820 dependent on the permissionwrite signal condition provided via path 550b.

KEYBOARD CIRCUIT

Referring now to FIG. 9, the keyboard circuit generally referred to bythe reference numeral 484 in FIG. 3, shall be described in greaterdetail. As previously mentioned, keyboard circuit 484 is preferably aconventional 10 digit keyboard which provides a serial digital output,the outputs preferably being group call via path 486, number via path488, up or more via path 490, down or back via path 492 and page callvia path 494, all of these outputs being provided to keyboard counter500 (FIG. 5). Although the keyboard circuitry 484 illustrated in greaterdetail in FIG. 9 is conventional, it shall be described in greaterdetail for purposes of clarity. The keyboard circuit 484 preferablycomprises a four line key input 823 which is a parallel BCD (binarycoded decimal) input. Each of the input lines 823a, 823b, 823c and 823dpreferably feeds a set/reset latch 824, 825, 826 and 827, respectively,which are conventional, so that when a key is depressed, the appropriatelatch 824 through 827 is set and stays set until released. The purposeof the keyboard circuit 484 is to make a BCD-to-binary conversion, theoutput of the keyboard circuit 484, as previously mentioned, being aserial signal comprising the number of pulses equivalent to the numberdepressed at the key input 823. A conventional oscillator, such as, byway of example, a 5 megahertz oscillator generates a master signal inparallel to the clock input of a conventional JK flip-flop 829 and toone input of a two input NAND gate 830. Flip-flop 829 and NAND gate 830,as will be described in greater detail hereinafter, preferably comprisea switch for turning the output of oscillator 828 to the balance of thecircuit on and off, oscillator 828, however, being a continuouslyrunning oscillator. Flip-flop 829 and NAND gate 830 insure that theoutput line does not start with a partial cycle. A pair of counters 831and 832 comprise a programmable decade counter which together provide adivide-by-10 to divide-by-one million counter. Programmable counter 831is preferably a conventional programmable counter of the typemanufactured by Mostec under the designation MK5009P, with counter 832being a conventional divide-by-10 decade counter of the typemanufactured by Texas Instruments under designation SN74160N. The outputfrequency of the programmable decade counter 831- 832 is preferablyapplied to a conventional key counter 833 such as the type manufacturedby Texas Instruments under designation SN74193, which is preferablypreloaded to a number equal to the keyboard input value from latches824, 825, 826 and 827. The counter 833 preferably only contains onedigit at a time and is preferably preloaded with the most significantdigit first. Key counter 833 then preferably counts down to 0 at theinput frequency supplied from programmable decade counter 831-832 andprovides a signal to flip-flop 829 via path 834 to reset flip-flop 829to its off state so that, therefore, no output will be provided fromflip-flop 829 to NAND gate 830 and, accordingly, gate 830 will notprovide the master clock output from oscillator 828 to counter 832, thuseffectively shutting off the input frequency. As a result, the totalnumber of pulses supplied to the keyboard counter 833 input during thecount cycle is equal to the keyboard input digit. In the row grabbingsystem 10 being presently described by way of example, five digits arepreferably chosen as being descriptive of the group and page, with thefirst two digits comprising the group and the last three digitscomprising the page so that the keyboard number input through thekeyboard 484 to the system 10 is a five digit number containing thisinformation. Accordingly, the first digit depressed is the mostsignificant digit and, for example, if it is a one, it is equal to10,000 pulses. In this instance, programmable decade counter 831-832would be a divide-by-10,000 counter so that the output signal present onpath 835 from the carry output of decade counter 832 would be equal to10,000 times the input signal on path 836 to key counter 833, the signalon 836 being the output of negative OR gate 837, whose input is in turnconnected to the output of NAND gate 838, whose inputs are in turnconnected to the output of NAND gate 839 and programmable counter 831.This cycle repeats for each digit for a total of five cycles, in theexample given, with programmable decade counter 831-832 being programmedto divide by one less decade for each successive digit; for example, inthe example given, to divide-by-10,000 for the most significant digit,then to divide-by-1,000 for the next digit, then to divide-by-100 forthe next digit, then to divide-by-10 for the next digit, and finally todivide-by-1 for the least significant digit. The inputs to programmablecounter 831 are preferably connected to the output of a conventionaldigit counter 840, such as the type manufactured by Texas Instrumentsunder designation SN74193N, whose output programs programmable counter831. Digit counter 840 is preferably initially set .Iadd.to .Iaddend.4which programs counter 831 to divide-by-10,000. Every time a cycle iscompleted on key counter 833, its output causes digit counter 840 tocoun down one digit to reprogram programmable counter 831. For example,in the example given, at the end of the most significant digit, digitcounter 840 would count down one digit to 3 from 4, resettingprogrammable counter 831 to divide-by-1,000, and so forth as the cyclerepeats with each successive digit. In other words, the binary output ofdigit counter 840 becomes the exponent of the programmable decadecounter 831.

PROGRAM COUNTER CONTROL

A conventional oscillator 844, such as 50 hertz in the example given,preferably provides the clock signal to a program counter 846, such as aconventional Texas Instrument model no. SN74160N, which establishes theprogram steps. The binary output of program counter 846 is preferablyconverted to decimal by conventional binary-to-decimal decoder 848, suchas a conventional Texas Instrument SN7442AN. Each output line of decoder848 preferably corresponds to one of the steps of a preferably ten stepkey examination program. The keyboard preferably consists of digits 0 to9 and three special keys labeled up, down and call. The key input 823preferably provides 16 binary values only 10 of which are used fordigits 0 through 9, three of the remaining six values preferably beingutilized for the special keys. The conventional decode networkcomprising NAND gates 851, 853, 855, and 857 and negative NAND gates 859and 861, decodes the input signal to determine if the key depressed isan up, down, call, or a number (one of the digits 0 through 9). If anup, down, or call key is depressed, a pulse will be present on path 852in the logic arrangement selected by way of example. This pulse presenton path 852 will preload digit counter 840 with the number 4 and willprovide a keyboard register enable signal which, as will be described ingreater detail hereinafter, will cause the keyboard register 910, 912,914 (FIG. 10) to accept the number previously generated. It should benoted, that in the system illustrated by way of example, digit counter840 must preferably be preset when the system 10 is turned on bydepressing the call key initially; thereafter, the call key is depressedafter the requested five digit number has been inputed. The initialdepression of the call key in this instance, as previously mentioned,establishes the required initial conditions for the system 10 bypreloading digit counter 840 with the number 4 so that programmablecounter 831 is initially programmed to divide-by-10,000. If the down keyis depressed, in addition, a pulse will be present on path 854 for thelogic chosen, to decrement the keyboard counter 500 (FIG. 10) by 1.Similarly, if the up key is depressed subsequent addition to the callkey, a pulse will be present on path 856, which is provided as one inputto a two input NOR gate 863 to provide an output pulse on path 865 toincrement the keyboard counter 500 (FIG. 10) by 1. If a number isdepressed, a pulse is present on path 858 from the output of negativeNAND gate 867 which pulse is provided to flip-flop 829 to turn onflip-flop 829 to initiate the pulse counting cycle previously describedby providing an output pulse to NAND gate 830 to permit the pulse outputof oscillator 828 to be passed to the clock input of decade counter 832which together with programmable counter 831, key counter 833 anddigital counter 840, as previously mentioned, accomplishes the pulsecounting cycle. A keyboard counter clear pulse is provided via path 860to the keyboard counter 500 (FIG. 10) when a number is depressed after anon-number condition. This is accomplished in the following manner. Apreset pulse is provided to a conventional JK flip-flop 864 via path 862when a call key, an up key, or a down key is depressed, this conditionbeing decoded by decoder 850. A pulse is present on path 866 when anumber is depressed, this condition also being decoded by decoder 850.Flip-flop 864 enables a NAND gate 870 when it is preset so that thepulse present on path 866 when a number is depressed will be passedthrough NAND gate 870 to provide the keyboard counter clear pulse onpath 860. The trailing edge of the pulse present on path 866 clearsflip-flop 864 so that subsequent number pulses provided via path 866will not issue a keyboard counter clear pulse on path 860 unlessflip-flop 864 is again preset by first receiving a pulse on path 862.

The keyboard input circuitry also preferably includes conventionalbounce rejection circuitry in initiating the program step operation ofkey processing. A four input NAND gate 874 is connected to input lines823a, 823b, 823c, and 823d and provides an output when all the key inputlines are high which preferably indicates that no key has beendepressed. When any key is depressed, the output of gate 874 preferablygoes low. When the depressed key has been released, the output of gate874 returns to high which triggers conventional single-shot 876 to fire.At the end of the single-shot pulse, which is preferably chosen to belong enough to allow bounce rejection and short enough to allow anacceptable key depression interval, such as approximately 50milliseconds, a JK flip-flop 878 is set which then enables programcounter 846 which, as previously mentioned, starts the ten step keyprocessing program operation. Flip-flop 878 is then preferablyautomatically reset by the last step of the program as indicated by asignal provided from decoder 848 to the preset input of flip-flop 878. Anegative NOR gate 880 is connected in parallel to the output of keycounter 833 and inhibits the triggering of single-shot 876 if any key isdepressed.

Referring now to FIG. 10, a portion of the memory input control systemillustrated in the block diagram of FIG. 5 and generally described withreference thereto shall be described in greater detail hereinafter. Thekeyboard counter 500 as shown and preferred in FIG. 10 consists of fiveconventional cascaded four bit up/down counters 900, 902, 904, 906 and908 which provide a 20 bit binary output in toto. Selected outputs fromthe counters 900 through 908, inclusive, are provided to conventionallatches 910, 912 and 914, latches 910 and 912 being, by way of example,the type manufactured by Texas Instruments under the designationSN74100N and latch 914, by way of example, .[.if.]. .Iadd.is .Iaddend.ofthe type manufactured by Texas Instruments under designation SN7475N.The output of counters 900, 902, 904, 906 and 908 is the binaryequivalent of the entire keyboard input number with the leastsignificant bit preferably being contained in counter 900 and the mostsignificant bit preferably being contained in counter 908. Counter 900and 902 provide the least significant bits to latch 910, counters 904and 906 provide the next .Iadd.significant .Iaddend.bits to latch 912and counter 908 provides the most significant bits to latch 914, latches910, 912 and 914 comprising the keyboard register which is enabled by asignal present on path 852, which is provided as previously described.Similarly, the up, down and clear signals for counter stages 900 through908, inclusive, are provided via path 865, 854 and 860, respectively, inthe manner previously described with reference to FIG. 9. Counter stages900 through 908 are preferably, by way of example, of the typemanufactured by Texas Instruments under designation SN74193. It shouldbe noted that in the example given although a 20 bit binary output isprovided by counter stages 900 through 908, inclusive, only 17 bits arepreferably actually utilized to provide the keyboard input number.Latches 910, 912 and 914 are loaded and store this keyboard number uponreceipt of the keyboard register enable signal via path 852.

As was previously mentioned with respect to FIG. 5, the selected pageoutput of latches 910, 912 and 914 associated with keyboard counter 500is provided to multiplexer 506 which, as shown and preferred in FIG. 10,comprises a two stage integrated circuit multiplexer 916-918. In theexample given, the multiplexer 506 comprises two stages 916 and.[.198.]. .Iadd.918 .Iaddend.because the practical limits of availableintegrated circuit multiplexes are 16 bits per package or chip.Accordingly, if a 17 bit multiplexer is available one could be utilizedinstead of the two stages 916 and 918. Stage 916, by way of example, ispreferably of the type manufactured by Texas Instruments underdesignation SN74150N and stage .[.916.]. .Iadd.918 .Iaddend.is, by wayof example, of the type manufactured by Texas Instruments underdesignation SN74151AN. As was previously described with reference toFIG. 5, nultiplexer 506 provides a serial output of the selected pageaddress via path 508 by combining the outputs of stages 916 and 918 inconventional fashion through negative NOR gate 920 which provides oneinput via path 508 to exclusive or gate 514, the other input to gate 514being provided via the data line 408. As also shown and preferred inFIG. 10, flip-flop 516 is a conventional JK flip-flop such as the typemanufactured by Texas Instruments under the designation SN74S113N.

As was previously mentioned, with respect to FIG. 5, the other input tomultiplexer 506 is provided from the page address counter 510 whichpreferably provides five bits for the page address, by way of example.Counter 510 is a two-stage counter comprising stages 922 and 924, onceagain, for the reason that the practical limit of such integratedcircuit chips is four bits in one package or chip. Accordingly, if afive bit counter can be obtained it can readily replace the two stages922 and 924. Thus, stage 922 is a four bit counter, such as the typemanufactured by Texas Instruments under designation SN74161N, by way ofexample, and stage 924 is a conventional flip-flop such as the typemanufactured by Texas Instruments under the designation SN7474N,flip-flop 924 adding one more bit to the four bit count of counter 922.As was previously mentioned, counter stages 922 and 924 advance themultiplexer 506, which is accomplished in the following fashion. Theoutput of stages 922 and 924 of counter 510 is provided to the inputs ofa two input conventional negative NAND gate 926, the output of stage 924being provided to one input and the output of stage 922 being providedto the other input. Gate 926 preferably functions as a simple decoderwhich turns the appropriate multiplexer stage 916 or 918 off while theother one is on. Counter stages 922 and 924 are cleared by thehorizontal sync signal provided via path 406. In the arrangementillustrated in FIG. 10, multiplexer stage 918 is first utilized and thenmultiplexer stage 916 is utilized, stage 918 being selected and stage916 being off as long as the output of decoder 926 is low and the outputof an inverter 928 connected thereto is high, the output of inverter 928being provided to stage 918 and the output of decoder 926 being provideddirectly to stage 916. When the count of stage 922 and 924 of counter510 reaches 8, then the output of decoder 926 preferably goes high andthe output of inverter 928 preferably goes low which turns the stage 918off and selects stage 916. As was previously mentioned, the output ofpage address counter 510 is also preferably provided to anotherconventional multiplexer 522, one input to multiplexer 522 being thehard-wired connection of the user address 524 illustratively representedby the switches and associated pull-up resistor banks 932 and 934, whichare conventional, to provide a high in the off condition and to providea low when a particular connection is hard-wired. Multiplexer 522 ispreferably identical in construction and operation to multiplexer 506and, similarly, comprises stages 916a and 918a which are identical instructure and operation with stages 916 and 918 of multiplexer 506 withthe exception that multiplexer stage 916a or 918a is selected by thelast stage 924 of the page address counter 510 without decoding via path930 or 931, with stage 916a being on for the first 16 counts then stage918a being on for the remaining five counts, 21 bits being preferablyassigned to the overall function. Thus, the page address counter 510outputs are provided in parallel to stages 916 and 918 of multiplexer506 and to stages 916a and 918a of multiplexer 522.

As was also previously mentioned with respect to FIG. 5, the selectedgroup address 502 is provided in parallel from appropriate stages oflatches 910, 912 and 914 of the keyboard counter 500.

Thus, it has been described how the page address signal is provided viapath 518 and the user address OK signal is provided via path 532 fromflip-flop 530 which, as shown and preferred, is another conventional JKflip-flop, such as the type manufactured by Texas Instruments under thedesignation SN74S113N. As was previously mentioned with reference toFIG. 5, the direct address OK signal provided via path 538 is providedto another flip-flop 536, such as another conventional JK flip-flop ofthe type similar to flip-flop 530. As was previously mentioned withrespect to FIG. 5, a bit one gate signal is provided via path 534 fromdecoder stage 940-942 which comprises negative NAND gate 940 and NANDgate 942 which decodes the page address counter 510 outputs to give a 1on path 534 at the K input to JK flip-flop 536 during the first bit orcount of the page address clock provided via path 512 if a 1 exists onthe data line 408 at that time, the data line 408 being provided oneinput to gate 942 of decoder 940-942. As was previously mentioned, itshould be noted that the first two digits of the five digit keyboardinput number is preferably the selected group 502 and the last threedigits are the selected page 504, with a total of seven bits preferablybeing provided for the group and 10 bits for the page information for atotal of 17 bits for the five digit keyboard input number.

Referring now to FIG. 11 which is a detailed logic schematic of thebalance of the memory input control system which has been previouslygenerally described with reference to FIG. 6, and referring initially topermission write logic 482, this logic 482 preferably comprises aconventional flip-flop 960 which provides a one television scan linedelay (approximately 63 microseconds) of the user address OK signalprovided via path 532 to the flip-flop 960. The output of flip-flop 960is preferably provided via path 961 to one input of a NAND gate 962whose other input is the permission bit line 480, NAND 962 preferablyproviding a low output when both the permission bit line 480 is high andthe output of flip-flop 960 is high. As shown and preferred for thelogic chosen, the output of gate 962, which is the permission writesignal, is inverted by an inverted 964 to provide a high signal on thepermission write line 550b during the permission write mode. This highoutput signal level is also provided in parallel to one input of a twoinput NAND gate 966 whose other input is the master clock A signalprovided via path 426 to provide a write clock or command signal viapath 550a to the permission memory 462. Permission memory 464 ispreferably a conventional integrated circuit, such as the typemanufactured by Signetics under the designation 2602B. Multiplexer 552which selectively provides the selected group input 502 to thepermission memory 464 preferably comprises two integrated circuit stages970 and 972 such as, by way of example, the type manufactured by TexasInstruments under the designation SN74157N. The bit counter 554 whichprovides another selectable input to multiplexer stages 970 and 972 ofmultiplexer 552 preferably comprises two conventional four bit counters974 and 976, such as the type manufactured by Texas Instruments underthe designation SN74161N, which are clocked by the clock A signal andswitched on by a negative NAND 978 contained in the permission writelogic 482. During the permission write mode, the inputs to gate 978 arethe permission write signal output of gate 962 and the clock A signal.Permission memory 462 is preferably a static MOS memory, such as onehaving a 1024 bit capacity arranged in a one-bit-by-1024 bit array.Permission memory 462 preferably holds its content even when the system10 has been turned off as a result of a low potential battery signal,such as one provided from a plus 4.5 volt battery 463 when the system isturned off. When the system is on, power is preferably applied to memory462, from a conventional plus 6 volt source 465 which charges the plus4.5 volt battery 463 and supplies power to permission memory 462.

Now describing the memory write logic 450, the permission bit present onpath 480 is preferably inverted by an inverter 982, for the logic chosenby way of example, and provided as one input to a two input NAND gate980 whose other input is the error check OK signal provided via path436. The output of gate 980 is preferably low when the error check OKsignal is present on path 436 and permission is not set. The output ofgate 980 is inverted for the logic chosen by way of example by inverter984 to provide one input to another two input NAND gate 986 containedwithin the memory write logic 450. Memory write logic 450 alsopreferably comprises another two input NAND gate 988 which receives asits inputs the delayed direct address OK signal present on path 562 andas the other input thereto the delayed user address OK signal providedvia path 961, and provides a low output if the user address is OK asindicated by the signal on path 961 and the direct address bit was setas indicated by the signal on path 562. Memory write logic 450 alsopreferably includes another two input NAND gate 990 which receives asone input the delayed page address OK signal provided via path 560 andas the other input thereto the permission OK signal provided via path556 from permission memory 462 and provides a low level output when boththese inputs are asserted. The output of gate 988 is provided as oneinput to a conventional two input negative NOR gate 992 and the outputof gate 990 is provided as the other input to gate 992 which preferablyhas a high output when either the user address is OK and the directaddress bit is set or when the page address is OK and permission is OK.The output of gate 992 is provided as one input to NAND gate 986 whoseother input, as previously described, is provided from the invertedoutput of gate 980. The output of gate 986 is, accordingly, preferablyhigh when an output is received from both gates 992 and 980, viainverter 984. The output of gate 986, which is the memory control readsignal provided via path 446, is preferably high during the memory readmode and low during the memory write mode for the main memory 464.Memory logic 450 also preferably includes a negative NAND gate 994 whichreceives as one input the output, in parallel, of gate 986 and as theother input the load memory clock provided via path 708 so that thisclock signal provided via path 708 is present at the output of gate 994during the memory write mode for the main memory 464 and is inverted,preferably, by inverter 996 and provided via path 995 to main memory 464to clock the memory 464.

Referring now to FIG. 12, the memory and output processing portion ofthe receiver portion 28 of the row .[.grabbling.]. .Iadd.grabbing.Iaddend.system 10 of the present invention shall be described, thisportion having previously been generally described with reference toFIGS. 3 and 6. The serial memory 456 preferably comprises theconventional one line shift register 457, such as the type manufacturedby Signetics under the designation 2502B, which is preferably driven bya two phase clock 1,000, the phase 1 output clock to shift register 457being indicated by reference numeral 1,001 and the phase 2 output clockto shift register 457 being indicated by output line 1,003. Two phaseclock generator 1,000, which is preferably conventional, comprises aconventional divide-by-2 flip-flop 1,002 whose clock input is thedelayed clock A signal present on path 1,004, the clock A signal on path1,004 being preferably delayed a fraction of a clock period. Flip-flop1,002 preferably serves alternately to enable either a two input NANDgate 1,006 or another two input NAND gate 1,008, the other input to gate1,006 being a delayed output of the inverted flip-flop 1,002 output. Asa result, the output of gate 1,006 is preferably low only during thedelay interval of the delay network comprising inverters 1,010 and1,012. Thus, the output of gate 1,006 is a narrow negative going pulsewhich occurs every other clock cycle. Similarly, the output of gate1,008, whose other input is provided via another delay networkcomprising inverters 1,014 and 1,016, provides a similar narrow negativegoing pulse, but which is staggered with the pulse train from gate1,006. The outputs of gates 1,006 and 1,008 are provided to aconventional dual clock driver 1,018, such as the type manufactured byNational Semiconductor under the designation MH0026CN, which amplifiesthe two clocks and supplies them to shift register 457 via path 1,001and 1,003 at a higher voltage level with a relatively high current drivecapability, shift register 457 being strobed by conventional two phaseclock 1,000.

Multiplexer 472, which selects the row address from the row latch 470 inthe main memory write mode and from the row address counter 474 in thememory read mode, preferably comprises a conventional four bitmultiplexer 1020, such as the type manufactured by Texas Instrumentsunder the designation SN74157 and a conventional one bit multiplexermade up of NAND gates 1022 and 1026, negative NOR gate 1024 and inverter1028 connected in conventional fashion to function as a one bitmultiplexer which together with multiplexer stage 1020 function as afive bit multiplexer 472.

The main memory 464, which is preferably conventional, preferablycomprises seven stages 1030, 1032, 1034, 1036, 1038, 1040 and 1042, witheach stage preferably being a 1024-by-1 bit array, such as the typemanufactured by Signetics under the designation 2602B, with the mostsignificant bit preferably being contained in stage 1030 and the leastsignificant bit preferably being contained in stage 1042. As shown andpreferred, there is a different input line for each stage 1030 through1042, inclusive, with the input lines being provided from the characterlatch 468, which is preferably a conventional character latch such asthe type manufactured by Texas Instruments under designation SN74100N, adifferent input line from character latch 468 being provided for eachstage 1030 through 1042, inclusive, for a total of seven paralleloutputs from character latch 468. Each stage 1030 through 1042,inclusive, preferably stores one specific bit of every character withstage 1042, as was previously mentioned, storing the least significantbit of every character and stage 1030 preferably storing the mostsignificant bit of every character. The main memory 464 portion alsopreferably includes a conventional two input NAND gate 1046 which turnson the memory write pulses present on path 995, provided thereto throughinverter 1047 for the logic chosen, during the precise periodcorresponding to the 32 characters of data the other input gate 1046being the memory gate signal provided via path 740. This modififiedsignal is provided via path 1044 to all stages 1030 through 1042,inclusive, of main memory 464. As shown and preferred in FIG. 12, thefive row address line parallel output of multiplexer 472 is preferablyconnected in parallel to all stages 1030 through 1042, inclusive, ofmain memory 464. Similarly, five character address lines from characteraddress counter 454 are preferably connected in parallel to all stages1030 through 1042, inclusive, of main memory 464. The character addresscounter 454, which provides the character address to main memory 464,preferably comprises a four bit conventional binary counter 1050, suchas the type manufactured by Texas Instruments under the designationSN74161N, and a conventional divide-by-two flip-flop 1052, such as thetype manufactured by Texas Instruments under designation SN7474N, forthe fifth bit to provide a five bit character address counter 454. Ifdesired, of course, a single five bit counter could be utilized. Thecharacter address counter for character counter 454 also preferablyincludes a conventional decoder gate 1054 which preferably provides alow level output on path 1126 during the occurrence of the charactertime corresponding to character 32.

Referring now to FIG. 13, the balance of the memory and output processorportion of the receiver portion 28 of the row grabbing system 10 of thepresent invention shall be described in greater detail, this portionhaving previously been generally described with reference to FIGS. 3, 6and 7. Line counter 572 preferably compirses a four bit conventionaldivide-by-13 counter 1056, such as the type manufactured by TexasInstruments under designation SN74163N, having parallel binary outputwhich is preferably decoded by a NAND gate 1058 which provides a lowlevel output pulse after the thirteenth count as one input to a twoinput negative NOR gate 1060 and, in parallel, via path 576 to the rowcounter 474. In the example given, a row, which is preferably thecontents of a pseudo video scan line 12, is preferably described ascomprising 13 conventional television scan lines. The other input togate 1060 is the inverted vertical sync signal provided via path 404.The output of gate 1060 is preferably inverted by an inverter 1062 andapplied to the clear input of counter 1056. This serves to reset theline counter 572 every 13 count or row and also at the vertical sync.The output of decoder gate 1058, as previously described is also theclock input of the row counter 474.

Row counter 474 preferably comprises a four bit conventional binarycounter 1063, such as the type manufactured by Texas Instruments underthe designation SN74161N, which is clocked by the row clock providedfrom gate 1058 on path 576. Counter 1063 is initially preset to a countof 15 or 13 depending on if it is set up for 16 or 12 rows,respectively. The clear input of counter 1063 is preferably connected tothe output of a D-type flip-flop 1064 which is initially cleared duringthe vertical sync period. At the occurrence of the first output pulsefrom decode gate 1058 (which is provided in parallel to the clock inputof flip-flop 1064, as well as to counter 1063) which occurs after thevertical sync, flip-flop 1064 is clocked. Prior to flip-flop 1064 beingclocked, the output of flip-flop 1064 is low causing counter 1063 to bepreset. After the clocking of flip-flop 1064, counter 1063 is allowed tocount and continues to count continuously until reset at the beginningof the next field, which is one full vertical scan. Row counter 474 alsopreferably includes another conventional D flip-flop 1065 which ispreferably utilized to generate a vertical unblanking signal. During 16row operation, flip-flop 1065 is initially cleared by the vertical syncsignal present on path 404. This 16 row operation is indicated byposition 1070a of switch 1070, 12 row operation being indicated byposition 1070b of switch 1070. At the start of the first row, the carryoutput of counter 1063, as inverted by conventional inverter 1066,clocks flip-flop 1065 whose output then goes high. The output offlip-flop 1065 remains high until counter 1063 completes 16 counts more,for 16 row operation, at which time the output of flip-flop 1065 is thenclocked low.

During 12 row operation, which is switch position 1070b, counter 1063 ispreset to 13 at the vertical sync as opposed to 15 which is utilized for16 row operation. At the third subsequent count after preset, the outputof counter 1063 clocks flip-flop 1065 so that the output of flip-flop1065 goes high. When counter 1063 counts to 12, in this instance, aconventional NAND gate 1068, which is connected in parallel to theoutput of counter 1063, decodes this value of 12 and generates a lowoutput which, through switch position 1070b, clears flip-flop 1065. As aresult, flip-flop 1065, during either 12 row or 16 row operationprovides a high output on path 1072 to NAND gate 592 during the timethat valid rows are generated.

As was previously mentioned with reference to FIG. 7, the paralleloutput of line counter 1056 is also provided in parallel to the inputsof a conventional character generator 570, such as the type manufacturedby Signetics under the designation 2525N in a standard format, charactergenerator 570 preferably being a conventional read only memory charactergenerator whose data input is the parallel data output 564 of memory464. The output of character generator 570, as was previously mentionedwith reference to FIG. 5, is provided to multiplexer 580, which ispreferably a conventional multiplexer, such as the type manufactured byTexas Instruments under the designation SN74151An, the output ofmultiplexer 580 being the video signal provided via path 590 to NANDgate 592 and, therefrom, through an exclusive or 1120 (functioning as aninverter) of the blanking logic 594, to path 598 as the video outputsignal.

Referring now to the column counter 442, this counter 442 preferablyincludes a pair of inverters 1074 and 1076 which provide a predetermineddelay, such as 100 nanoseconds in the clock B signal provided via path430, this delay time preferably representing a fraction of the clockperiod. The delayed clock B signal is preferably supplied to one inputof a two input exclusive or gate 1078 whose other input is directlyconnected to the clock B input provided via path 430. Exclusive or gate1078 preferably provides an output only during the period of time thatthe delayed clock B signal overlaps the undelayed clock B signal. Thisoccurs twice per clock period and, as a result, two output pulses areavailable from gate 1078 for each input pulse. Accordingly, inverters1074 and 1076 and gate 1078 form a conventional frequency doubler. Thedouble frequency output of gate 1078, which is twice the clock Bfrequency, is utilized as the clock input for a conventional divide-by-8counter 1080, such as the type manufactured by Texas Instruments underthe designation SN74161N, which is a four bit binary counter connectedas a divide-by-8 counter, although if desired a conventional divide-by-8counter could be utilized. This double frequency clock signal ispreferably utilized as the clock for counter 1080 only during 64character operation. During 32 character operation, that is 32characters per video row versus 64 characters per video row, counter1080 is clocked directly by the clock B signal provided via path 430.Counter 1080, which preferably provides the least significant bit viapath 1081 to multiplexer 580 and the most significant bit via path 1116to the blanking logic 594, is cleared by the output of a conventionalflip-flop 1082 which flip-flop 1082 is clocked by the character 2 timingsignal output provided via path 685 from decoder 412. Flip-flop 1082 isinitially cleared by the horizontal sync signal provided in parallel viapath 406 and then is set at the start of character 2 by the signalprovided via path 685 from decoder 412. This serves to keep counter 1080in the cleared state until the time corresponding to the beginning ofthe second character of the pseudo video scan line 12. This provides aninitial delay for the displayed characters to provide a left-hand marginfor the video display. The three least significant bits from counter1080 preferably provide the addressing inputs for multiplexer 580; thus,they supply the divide-by-8 count sequence needed by multiplexer 580.The most significant bit provided from counter 1080 via path 1116 toblanking logic 594 preferably alternates states, that is from 1-to-0to-1-to-0 etc., at the character rate.

Multiplexer 440 is preferably a conventional multiplexer whichpreferably includes an inverter 1098 which, together with conventionalNAND gates 1094 and 1096, selects the appropriate clock for thecharacter counter 454 during the read and write modes of the memory 464,the character clock during the memory write mode being provided fromdecoder 412 and during the memory read mode being provided from columncounter 442. During the memory read mode, line 446 is high and one inputto NAND gate 1094 is high while one input to NAND gate 1096 is low. Inthis condition, the clock available at the other input to NAND gate 1094is selected and appears at the output of gate 1094 and at the output ofnegative NOR gate 1102 which has one input connected to the output ofgate 1094 and the other input connected to the output of gate 1096, theinput that is connected to the output of gate 1094 being connected inparallel to the clock B input. One input to gate 1096 is the output ofanother two input NAND gate 1104. During the memory write mode, line 446is low, one input of NAND gate 1096 is high and the clock available atthe output of NAND gate 1104, which has the memory gate signal providedvia path 740 as one input thereto and the change memory address signalprovided via path 710 as the other input thereto, is utilized as thecharacter counter clock. The write mode character counter clock fromNAND gate 1104 is obtained from the change memory address line 710 fromdecoder 412 as gated on by the memory gate line 740 from decoder 412.The memory gate on path 740 serves to allow the number of write clocksthat corresponds exactly to the 32 data characters written into memory464. During the memory read mode, the character address counter clock isprovided by NOR gate 1092. This clock is generated by decoding theoutput of counter 1080 provided via path 1116, such that one clock pulseis generated for each eight counts of the counter 1080. A differentdecode is normally preferably required for 32 and 64 characteroperation.

The decoding of the output of counter 1080 is accomplished by NAND gate1086, whose inputs are the three least significant bits of the counter1080 output, and negative NAND gates 1088 and 1090. The differentdecodes are required because a fixed propagation delay represents adifferent proportion of character width in 64 character operation ascompared to 32 character operation. Whichever character address counterclock output is selected preferably appears inverted at the output ofnegative NOR gate 1102 and non-inverted through inverter 1106 on path1107 to character counter 454.

BLANKING LOGIC

Now the blanking logic 594 will be described in greater detail withreference to FIG. 13. Blanking is accomplished by NAND gate 592, aspreviously mentioned. The video output from multiplexer 580 provided viapath 590 is supplied to one of four inputs of NAND gate 592. Thevertical unblanking signal is provided to another input of NAND gate 592from flip-flop 1065 via path 1072. The memory control signal provided onpath 446 is provided in parallel to another input of NAND gate 592 toprovide unblanking during the memory read mode. Lastly, the horizontalunblanking signal is provided to NAND gate 592 via path 1108, thehorizontal unblanking signal on path 1108 being generated by aconventional RS flip-flop 1110-1112 arrangement. During 64 characteroperation flip-flop 1110-1112 is preferably set by the output of anegative NAND gate 1114 which goes high when the character 3 timingpulse of decoder 412 is present and counter 1080 has counted to 8, asindicated by the signal present on the most significant bit line 1116,as inverted by inverter 1117. During 32 character operation, thecharacter 4 timing pulse from decoder 412 is preferably utilized in lieuof the character 3 timing pulse. The setting of flip-flop 1110-1112provides the horizontal unblanking start signal on path 1108 which ishigh when the horizontal unblanking signal is present thereon. NegativeNAND 1118 terminates the horizontal unblanking signal by resettingflip-flop 1110-1112 when the character 40 timing pulse is present fromdecoder 412 and counter 1080 has counted to 8 as indicated by the signalon path 1116 as inverted by inverter 1117. As was previously mentioned,the output of NAND gate 592 is provided to exclusive or gate 1120 whichis conventionally utilized as an inverter, NAND gate 592 providing anoutput when video is present and all unblanking lines 1108,1072 and 446are asserted.

As shown and preferred in FIG. 13, another conventional flip-flop 1124is utilized to provide the left/right read address bit on path 1122 for64 character operation. Flip-flop 1124 is initially cleared by thehorizontal sync signal provided via path 406 so that output path 1122 isinitially low. When the character counter 454 completes a count of 32 asindicated by the signal provided via path 1126 to the clock input offlip-flop 1124, flip-flop 1124 is set so that output path 1122 goeshigh. Output path 1122 is utilized by main memory 464 to select adifferent set of 32 characters for the right hand side of the 64character display during 64 character operation. During 32 characteroperation, flip-flop 1124 does not come into play.

The balance of the circuitry associated with the receiver portion 28 ofthe row grabbing system 10 of the present invention has been adequatelydescribed with reference to the block diagrams of FIGS. 3 through 7 asit is conventional and readily understandable by one of ordinary skillin the art without further explanation, and accordingly, will not bedescribed in further detail.

By utilizing the row grabbing system 10 of the present invention,conventional television transmission techniques and distributionequipment can be utilized for transmission and reception of data whichhas been packed into pseudo video scan lines which look like aconventional TV scan line to television equipment but contain a completepacket of information suitable for display of an entire row of videoinformation, noise immunity between pseudo video scan lines is provideddue to all input logic being reset every sync pulse so that every pseudovideo scan line which is processed starts fresh and any loss ofsynchronization or the occurrence of a noise pulse will be preventedfrom disrupting more information than one pseudo video scan line or row,a grabbed frame may be updated on a row-by-row basis rather than anentire page by page basis, significant data transmission time andincreased data bit rate may be achieved and the update time can be muchgreater than in a conventional frame grabbing system, such as the typeutilizing conventional page-by-page video transmission.

It is to be understood that all logic described herein is conventionalunless otherwise specified.

It is to be understood that the above described embodiment of theinvention is merely illustrative of the principles thereof and thatnumerous modifications and embodiments of the invention may be derivedwithin the spirit and scope thereof, such as by utilizing a differenterror check scheme, such as one utilizing the sum of the numerical valueof each character present as the error check sum, providing for thetransmission of a color display, such as a color background for one ormore rows in the video display, as well as many other modifications thatwill occur to one of ordinary skill in the art.

What is claimed is:
 1. A real time frame grabbing system forsubstantially instantaneously providing a continuous video display of aselectable predetermined video frame of information on a video displaymeans from continuously transmittable video information comprising meansfor transmitting said video information as a plurality of pseudo videoscan lines, each of said pseudo video scan lines having a televisionvideo scan line format and capable of comprising a completeself-contained packet of digital information sufficient to provide anentire displayable row of video data characters, said pseudo video scanline having an associated transmission time equivalent to saidtelevision video scan line, said packet of digital informationcomprising at least address information for said displayable row anddata information for said displayable characters in said displayablerow, each of said pseudo video scan lines further comprising ahorizontal sync signal at the beginning thereof, said horizontal syncsignal providing a record separator between adjacent pseudo video scanlines, said transmitting means further comprising means for providing avertical sync signal after a predetermined plurality of pseudo videoscan lines have been transmitted, said pseudo video scan line being acomposite video signal, said system further comprising television signaldistribution means for distributing said transmitted composite pseudovideo scan line signals to said video display means for providing saidcontinuous video display.[...]..Iadd., and receiver means operativelyconnected between said television signal distribution means and saidvideo display means for processing said distributed composite pseudovideo scan line signals and capable of providing a displayable video rowsignal to said video display means from a pseudo video scan line signalpertaining to said selected frame for providing said continuous videodisplay, said receiver means comprising means for updating saidcontinuously video displayable selectable frame on a displayable videorow-by-row basis as said data portion of any of said displayablereceived distributed pseudo video scan line signals pertaining to saidselected frame is updated. .Iaddend.
 2. A real time frame grabbingsystem in accordance with .[.claim.]. .Iadd.claims 1 or 28.Iaddend.wherein said composite pseudo video scan line signal providedby said transmitting means comprises a three level signal having first,second and third signal levels with said digital data informationvarying between said second and third signal levels and said horizontalsync signal information being provided between said first and secondsignal levels.
 3. A real time frame grabbing system in accordance with.[.claim.]. .Iadd.claims 1 or 28 .Iaddend..[.further comprising receivermeans operatively connected between said television signal distributionmeans and said video display means for processing said distributedcomposite pseudo video scan line signals and.]. .Iadd.wherein saidprocessing means comprises means .Iaddend.capable of providing adisplayable video row signal to said video display means from each ofsaid pseudo video scan line signals pertaining to said selected framefor providing said continuous video display, a predetermined pluralityof displayable video rows comprising a displayable video frame ofinformation.
 4. A real time frame grabbing system in accordance withclaim 3 wherein said composite video scan line signal further comprisesclock signal reference frequency information, said receiver signalprocessing means comprising means for providing a master clock signaloutput in accordance with said reference frequency information and apredetermined data bit rate, and decoder means operatively connected tosaid master clock signal output for providing timing control signals forsaid receiver signal processing means indicative of predeterminedcharacter positions within said pseudo video scan line signal andpredetermined bit positions within a character for processing saiddistributed pseudo video scan line to provide said displayable video rowsignal therefrom.
 5. A real time frame grabbing system in accordancewith claim 3 wherein said receiver signal processing means comprisesmeans responsive to the occurrence of said horizontal sync signal foreach distributed pseudo video scan line for resetting said processingmeans in response to each detection of said horizontal sync signal,whereby noise immunity for said system is enhanced.
 6. A real time framegrabbing system in accordance with claim .[.3.]. .Iadd.1.Iaddend.wherein said .[.receiver.]. .Iadd.updating .Iaddend.meanscomprises means for updating said continuously video displayableselectable frame on a displayable video row-by-row basis dependent onthe real time data information content of said received pseudo videoscan .[.lines.]. .Iadd.line. .Iaddend.
 7. A real time frame grabbingsystem in accordance with claim .[.6.]. .Iadd.1 .Iaddend.wherein saidupdating means comprises memory means for retrievably storing saidcontinuously distributed pseudo video scan line data portion forproviding said displayable video row therefrom, said memory meansretrievably stored data portion being continuously updateable as saiddata portion of said pseudo video scan line signal associated therewithis updated.
 8. A real time frame grabbing system in accordance withclaim .[.3.]. .Iadd.1 or 28 .Iaddend.wherein each of said packets ofdigital information further comprises an error check information contentbased on at least the address and data information content of anassociated pseudo video scan line, said receiver signal processing meanscomprising error check means for obtaining an error check indicationfrom said distributed associated pseudo video scan line and comparingsaid error check indication with said error check information content ofsaid associated pseudo video scan line in accordance with apredetermined error check condition for providing a predetermined outputcondition signal when said error check condition is satisfied, saidreceiver signal processing means further comprising condition responsivemeans operatively connected to said error check means to receive saidpredetermined output condition signal therefrom when provided, saidcondition responsive means inhibiting the provision of said displayablevideo row from said associated pseudo video scan line signal when saidpredetermined output condition signal is not provided thereto. .[.9. Areal time frame grabbing system in accordance with claim 8 wherein saidreceiver means comprises means for testing said address informationportion of said distributed pseudo video scan line signal forsatisfaction of at least one predetermined signal reception condition,said address information testing means providing a predetermined outputcondition when said reception condition is satisfied, memory means forretrievably storing said pseudo video scan line data portion forproviding said displayable video row therefrom and delay means fordelaying the storing of said distributed pseudo video scan line signaldata portion for a sufficient interval to enable testing for said errorcheck condition and testing of said address information prior to storingof said pseudo video scan line data portion, said condition responsivemeans being further operatively connected to said address informationtesting means for inhibiting the storage of said data portion in saidmemory means when said predetermined output condition signals from saidtesting means are not provided thereto, whereby the provision of saiddisplayable video row from said associated pseudo video scan line signalis inhibited..].
 10. A real time frame grabbing system in accordancewith claim .[.9.]. .Iadd.1 .Iaddend.wherein said receiver means furthercomprises keyboard means for selecting said predetermined video frame tobe continuously displayed, said address information comprisinginformation corresponding to the frame associated with said distributedpseudo video scan line, said address information testing meanscomprising means for testing said frame information, said receptioncondition being correspondence between said frame information and saidselected frame. .[.11. A real time frame grabbing system in accordancewith claim 9 wherein a predetermined pseudo video scan line signalcontains permission information representative of predetermined frameswhich a video display means is authorized to receive for video displaythereof, said receiver means comprising means for storing saidauthorized frames, said address information comprising informationcorresponding to the frame associated with said distributed pseudo videoscan line, said address information testing means comprising means fortesting said frame information, said reception condition beingcorrespondence between said frame information and stored authorizedframe..].
 12. A real time frame grabbing system in accordance with claim.[.1.]. .Iadd.28 .Iaddend.wherein said system further comprisesprogrammable means for receiving said continuously transmittable videoinformation, retrievably storing said information, reformatting saidstored information into a desired pseudo video scan line format andcontinuously providing this reformatted information to said transmittingmeans a word at a time, said word comprising a pair of displayablecharacters. .[.13. A real time frame grabbing system in accordance withclaim 12 wherein said programmable means includes means for interleavingsaid reformatted pseudo video scan line information to provide pseudovideo scan line information corresponding to a common assigned row for aplurality of frames to said transmitting means before providing pseudovideo scan line information corresponding to a subsequent differentcommon assigned row for said plurality of frames to said transmittingmeans..]. . A real time frame grabbing system in accordance with claim12 wherein said transmitting means comprises a first-in-first-out serialword memory means having a storage capacity of a predetermined pluralityof words operatively connected to said programmable means for receivingsaid reformatted information word transmission therefrom, and means forcontrolling the strobing of data out of said first-in-first-out memorymeans operatively connected to said first-in-first-out memory means,said programmable means controlling the strobing of data into saidfirst-in-first-out memory means.
 15. A real time frame grabbing systemin accordance with claim 14 wherein said transmitter means comprises amaster clock signal generation means for controlling the bit rate oftransmission of said pseudo video scan line signals, bit counting meansoperatively connected to said master clock signal generation means forcounting said clock signal and providing an output pulse each time saidbit count corresponds to a predetermined common quantity of bits in adisplayable character, said output pulse representing the start of saidcharacter, means for generating a composite sync signal and verticaldrive signal, said master clock signal generation means synchronizingsaid bit rate with said composite sync signal, means operativelyconnected to said sync signal generation means for providing a frameenable signal at a predetermined vertical scan position after saidvertical drive signal, said means for controlling the strobing of dataout of said first-in-first-out memory means capable of receiving a readyto transmit data signal from said first-in-first-out memory means andcomprising condition responsive means operatively connected to said syncsignal generating means for receiving said composite sync signaltherefrom, said bit counting means for receiving said output pulsetherefrom, said frame enable signal providing means for receiving saidframe enable signal therefrom and said first-in-first-out memory meansfor receiving said ready to transmit data signal therefrom forcontrolling said strobing of data out from said first-in-first-outmemory means in response to said received signals for providing saiddata information portion for one of said pseudo video scan line signals.16. A real time frame grabbing system in accordance with claim 15wherein said transmitter means further comprises sync combining meansoperatively connected to said first-in-first-out memory means forreceiving said one pseudo video scan line signal data informationportion and to said sync signal generating means for receiving saidcomposite sync signal therefrom for providing said composite pseudovideo scan line signal to said distribution means. . A real time framegrabbing system in accordance with claim 16 wherein said transmittermeans further comprises a shift register means operatively connectedbetween said first-in-first-out memory means output and said synccombining means input, said shift register means further beingoperatively connected to said bit counting means output and said masterclock signal generating means output for loading said one pseudo videoscan line signal data portion from said first-in-first-out memory meansinto said shift register means in response to said bit counting meansoutput pulse, said shift register means shifting out said loaded onepseudo video scan line signal data portion for providing said dataportion to said sync combining means at a shift rate established by saidmaster clock signal.
 18. A real time frame grabbing system in accordancewith claim 17 wherein said transmitter means further comprises flip-flopmeans and character counting means having its input connected to saidbit counting means output for clocking said character counting means inresponse to said bit counting means output pulse for providing an outputpulse when a quantity of bit counting means output pulses correspondingto a predetermined total number of characters comprising one pseudovideo scan line signal has been counted for establishing a time periodcorresponding to said total number of characters, said charactercounting means output being connected to said flip-flop means forreceiving said character counting means output pulse and providing async burst gate signal output in response thereto, said flip-flop meansbeing further operatively connected to said sync signal generating meansfor receiving said composite sync signal, said flip-flop means being setby said character counting means output pulse and reset by saidcomposite sync signal, said transmitter means further comprising aselectable multiplexer means having a first input operatively connectedto said shift register means output and a second input operativelyconnected to said master clock signal generating means output forproviding a clock synchronizing burst signal thereto and further beingconnected to said flip-flop means output for switching between saidfirst and second inputs in response thereto, said multiplexer meansoutput being connected to said sync combining means input forselectively providing said first and second inputs thereto, said clocksynchronizing burst signal being selected during the interval of saidsync burst gate signal, said shift register means output being selectedwhen said sync burst gate signal output is not provided and said shiftregister means output is provided, said composite pseudo video scan linesignal further comprising said clock synchronizing burst signal for aninterval corresponding to said sync burst gate interval.
 19. A real timeframe grabbing system for substantially instantaneously providing acontinuous video display of a selectable predetermined video frame ofinformation on a video display means from a plurality of pseudo videoscan lines, each of said pseudo video scan lines having a televisionvideo scan line format and capable of comprising a completeself-contained packet of digital information sufficient to provide anentire displayable row of video data characters, said pseudo video scanline having an associated transmission time equivalent to saidtelevision scan line, said packet of digital information comprising atleast address information for said displayable row and data informationfor said displayable characters in said displayable row, each of saidpseudo video scan lines further comprising a horizontal sync signal atthe beginning thereof, said horizontal sync signal providing a recordseparator between adjacent pseudo video scan lines, said pseudo videoscan line being a composite video signal, said system comprising meansfor selecting said predetermined video frame to be continuouslydisplayed and means operatively connected to said video display meansand said frame selection means for processing said composite pseudovideo scan line signals and capable of providing a displayable video rowsignal to said video display means from each of said pseudo video scanline signals pertaining to said selected frame for providing saidcontinuous video display, a predetermined plurality of displayable videorows comprising a displayable video frame of information.[...]..Iadd.,said processing means comprising means for updating said continuouslyvideo displayable selectable frame on a displayable video row-by-rowbasis as said data portion of any of said displayable receiveddistributed pseudo video scan line signals pertaining to said selectedframe is updated. .Iaddend.
 20. A real time frame grabbing system inaccordance with claim 19 .Iadd.or 29 .Iaddend.wherein said processingmeans comprises means responsive to the occurrence of said horizontalsync signal for each pseudo video scan line for resetting saidprocessing means in response to each detection of said horizontal syncsignal, whereby noise immunity for said system is enhanced.
 21. A realtime frame grabbing system in accordance with claim 19 .Iadd.or 29.Iaddend.wherein said composite pseudo video scan line signal furthercomprises clock signal reference frequency information, said processingmeans comprising means for providing master clock signal output inaccordance with said reference frequency information and a predetermineddata bit rate, and decoder means operatively connected to said masterclock signal output for providing timing control signals for saidprocessing means indicative of predetermined character positions withinsaid pseudo video scan line signal and predetermined bit positionswithin a character for processing said distributed pseudo video scanline to provide said displayable video row signal therefrom.
 22. A realtime frame grabbing system in accordance with claim 19 wherein said.[.processing.]. .Iadd.updating .Iaddend.means comprises means forupdating said continuously video displayable selectable frame on adisplayable video row-by-row basis dependent on the real time datainformation content of said received pseudo video scan lines.
 23. A realtime frame grabbing system in accordance with claim .[.22.]. .Iadd.19.Iaddend.wherein said updating means comprises memory means forretrievably storing said pseudo video scan line data portion forproviding said displayable video row therefrom, said memory meansretrievably stored data portion being continuously updateable as saiddata portion of said pseudo video scan line signal associated therewithis updated.
 24. A real time frame grabbing system in accordance withclaim 19 .Iadd.or 20 .Iaddend.wherein each of said packets of digitalinformation further comprises an error check information content basedon at least the address and data information content of an associatedpseudo video scan line, said processing means comprising error checkmeans for obtaining an error check indication from said distributedassociated pseudo video scan line and comparing said error checkindication with said error check information content of said associatedpseudo video scan line in accordance with a predetermined error checkcondition for providing a predetermined output condition signal whensaid error check condition is satisfied, said processing means furthercomprising condition responsive means operatively connected to saiderror check means to receive said predetermined output condition signaltherefrom when provided, said condition responsive means inhibiting theprovision of said displayable video row from said associated pseudovideo scan line signal when said predetermined output condition signalis not provided thereto. .[.25. A real time frame grabbing system inaccordance with claim 24 wherein said processing means comprises meansfor testing said address information portion of said distributed pseudovideo scan line signal for satisfaction of at least one predeterminedsignal reception condition, said address information testing meansproviding a predetermined output condition when said reception conditionis satisfied, memory means for retrievably storing said pseudo videoscan line data portion for providing said displayable video rowtherefrom and delay means for delaying the storing of said distributedpseudo video scan line signal data portion for a sufficient interval toenable testing for said error check condition and testing of saidaddress information prior to storing of said pseudo video scan line dataportion, said condition responsive means being further operativelyconnected to said address information testing means for inhibiting thestorage of said data portion in said memory means when saidpredetermined output condition signal from said testing means are notprovided thereto, whereby the provision of said displayable video rowfrom said associated pseudo video scan line signal is inhibited..]. 26.A real time frame grabbing system in accordance with claim .[.24.]..Iadd.29 .Iaddend.wherein said selection means comprises keyboard means,said address information comprising information corresponding to theframe associated with said pseudo video scan line, said addressinformation testing means comprising means for testing said frameinformation, said reception condition being correspondence between saidframe information and said selected frame. .[.27. A real time framegrabbing system in accordance with claim 25 wherein a predeterminedpseudo video scan line signal contains permission informationrepresentative of predetermined frames which a video display means isauthorized to receive for video display thereof, said processing meanscomprising means for storing said authorized frames, said addressinformation comprising information corresponding to the frame associatedwith said pseudo video scan line, said address information testing meanscomprising means for testing said frame information, said receptioncondition being correspondence between said frame information and storedauthorized frame..]. .Iadd.28. A real time frame grabbing system forsubstantially instantaneously providing a continuous video display of aselectable predetermined video frame of information on a video displaymeans from continuously transmittable video information comprising meansfor transmitting said video information as a plurality of pseudo videoscan lines, each of said pseudo video scan lines having a televisionvideo scan line format and capable of comprising a completeself-contained packet of digital information sufficient to provide anentire displayable row of video data characters, said pseudo video scanline having an associated transmission time equivalent to saidtelevision video scan line, said packet of digital informationcomprising at least address information for said displayable row anddata information for said displayable characters in said displayablerow, each of said pseudo video scan lines further comprising ahorizontal sync signal at the beginning thereof, said horizontal syncsignal providing a record separator between adjacent pseudo video scanlines, said transmitting means further comprising means for providing avertical sync signal after a predetermined plurality of psuedo videoscan lines have been transmitted, said pseudo video scan line being acomposite video signal, said system further comprising television signaldistribution means for distributing said transmitted composite pseudovideo scan line signals to said video display means for providing saidcontinuous video display and programmable means for receiving saidcontinuously transmitted video information, retrievably storing saidinformation, reformatting said stored information into a desired pseudovideo scan line format and continuously providing this reformattedinformation to said transmitting means, said programmable meansincluding means for interleaving said reformatted pseudo video scan lineinformation corresponding to a common assigned row for a plurality offrames to said transmitting means before providing pseudo video scanline information corresponding to a subsequent different common assignedrow for said plurality of frames to said transmitting means. .Iaddend..Iadd.29. A real time frame grabbing system for substantiallyinstantaneously providing a continuous video display of a selectablepredetermined video frame of information on a video display means from aplurality of pseudo video scan lines, each of said pseudo video scanlines having a television video scan line format and capable ofcomprising a complete self-contained packet of digital informationsufficient to provide an entire displayable row of video datacharacters, said pseudo video scan line having an associatedtransmission time equivalent to said television scan line, said packetof digital information comprising at least address information for saiddisplayable row and data information for said displayable characters insaid displayable row, each of said pseudo video scan lines furthercomprising a horizontal sync signal at the beginning thereof, saidhorizontal sync signal providing a record separator between adjacentpseudo video scan lines, said pseudo video scan line being a compositevideo signal, said system comprising means for selecting saidpredetermined video frame to be continuously displayed and meansoperatively connected to said video display means and said frameselection means for processing said composite pseudo video scan linesignals and capable of providing a displayable video row signal to saidvideo display means from each of said pseudo video scan line signalspertaining to said selected frame for providing said continuous videodisplay, a predetermined plurality of displayable video rows comprisinga displayable video frame of information, said processing meanscomprising means for updating said continuously video displayableselectable frame on a displayable video row-by-row basis as said dataportion of any of said displayable received distributed pseudo videoscan line signals pertaining to said selected frame is updated, apredetermined pseudo video scan line signal containing permissioninformation representative of predetermined frames which a video displaymeans is authorized to receive for video display thereof, saidprocessing means comprising means for storing said authorized frames andfor testing said address information portion of said distributed pseudovideo scan line signal for satisfaction of at least one predeterminedsignal reception condition, said address information testing meansproviding a predetermined output condition signal when said receptioncondition is satisfied, said processing means further comprisingcondition responsive means operatively connected to said addressinformation testing means for inhibiting the storage of said distributedpseudo video scan line signal data portion in said authorized framestoring means when said predetermined output condition signal is notprovided thereto from said testing means, said address informationcomprising information corresponding to the frame associated with saiddistributed pseudo video scan line, said address information testingmeans comprising means for testing said frame information, saidreception condition being correspondence between said frame informationand stored authorized frame, whereby the provision of said displayablevideo row from said associated pseudo video scan line is inhibited inthe absence of authorization for display thereof. .Iaddend. .Iadd.30. Areal time frame grabbing system in accordance with claim 8 wherein saidreceiver means further comprises memory means for retrievably storingsaid pseudo video scan line data portion for providing said displayablevideo row therefrom and delay means for delaying the storing of saiddistributed pseudo video scan line signal data portion for a sufficientinterval to enable testing for said error check condition and testing ofsaid address information prior to storing of said pseudo video scan linedata portion. .Iaddend. .Iadd.31. A real time frame grabbing system inaccordance with claim 24 wherein said processing means further comprisesmemory means for retrievably storing said pseudo video scan line dataportion for providing said displayable video row therefrom and delaymeans for delaying the storing of said distributed pseudo video scanline signal data portion for a sufficient interval to enable testing forsaid error check condition and testing of said address information priorto storing of said pseudo video scan line data portion. .Iaddend.